PIC18F2320-I/SP Microchip Technology, PIC18F2320-I/SP Datasheet - Page 36

• Manufacturer Part Number: PIC18F2320-I/SP
• Description: IC MCU FLASH 4KX16 EEPROM 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2320-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI/I2C/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2220/2320/4220/4320
3.3.2
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered by setting the IDLEN
bit, modifying to SCS1:SCS0 = 01 and executing a
SLEEP instruction. When the clock source is switched
to the Timer1 oscillator (see Figure 3-5), the primary
oscillator is shut down, the OSTS bit is cleared and the
T1RUN bit is set.
FIGURE 3-5:
FIGURE 3-6:
DS39599G-page 34
T1OSI
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
Note:
CPU Clock
Note 1: T
Peripheral
PLL Clock
Program
Counter
Output
T1OSI
OSC1
Clock
SEC_IDLE MODE
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when try-
ing to set the SCS0 bit (OSCCON<0>),
the write to SCS0 will not occur. If the
Timer1 oscillator is enabled but not yet
running, peripheral clocks will be delayed
until the oscillator has started; in such sit-
uations, initial oscillator operation is far
from stable and unpredictable operation
may result.
Q1
Wake-up from Interrupt Event
OST
Q2
= 1024 T
PC
Q3
PC
Q4
TIMING TRANSITION FOR ENTRY TO SEC_IDLE MODE
TIMING TRANSITION FOR WAKE FROM SEC_RUN MODE (HSPLL)
OSC
Q1
; T
Q1
PLL
1
T
= 2 ms (approx). These intervals are not shown to scale.
OST
(1)
2
Q2
PC + 2
3
T
Clock Transition
OSTS bit Set
PLL (1)
Q3
4
Q4
5
PC + 2
6
Q1
1
2
7
When a wake-up event occurs, the peripherals continue
to be clocked from the Timer1 oscillator. After a 10 μs
delay following the wake-up event, the CPU begins exe-
cuting code, being clocked by the Timer1 oscillator. The
microcontroller operates in SEC_RUN mode until the
primary clock becomes ready. When the primary clock
becomes ready, a clock switch back to the primary clock
occurs (see Figure 3-6). When the clock switch is com-
plete, the T1RUN bit is cleared, the OSTS bit is set and
the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run.
Clock Transition
3
8
4
5
PC + 4
6
7
8
© 2007 Microchip Technology Inc.
Q2
Q3 Q4
Q1
PC + 6
Q2
Q3