PIC18F2320-I/SP Microchip Technology, PIC18F2320-I/SP Datasheet - Page 291

• Manufacturer Part Number: PIC18F2320-I/SP
• Description: IC MCU FLASH 4KX16 EEPROM 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2320-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI/I2C/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

RETURN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2007 Microchip Technology Inc.
Q Cycle Activity:
After Interrupt
operation
Decode
No
PC = TOS
Q1
operation
operation
Return from Subroutine
[ label ]
s ∈ [0,1]
(TOS) → PC;
if s = 1,
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
None
Return from subroutine. The stack
is popped and the top of the stack
(TOS) is loaded into the program
counter. If ‘s’= 1, the contents of the
shadow registers WS, STATUSS
and BSRS are loaded into their cor-
responding registers, W, STATUS
and BSR. If ‘s’ = 0, no update of
these registers occurs (default).
1
2
RETURN
0000
No
No
Q2
RETURN [s]
0000
operation
Process
Data
No
Q3
0001
pop PC from
operation
PIC18F2220/2320/4220/4320
stack
No
Q4
001s
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
C
REG
W
C
Q1
=
=
=
=
=
register ‘f’
Rotate Left f through Carry
[ label ]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f<n>) → dest<n+1>,
(f<7>) → C,
(C) → dest<0>
C, N, Z
The contents of register ‘f’ are
rotated one bit to the left through
the Carry Flag. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1
RLCF
Read
Q2
0011
1110 0110
0
1110 0110
1100 1100
1
C
RLCF
01da
Process
Data
Q3
REG, W
register f
DS39599G-page 289
f [,d [,a]]
ffff
destination
Write to
Q4
ffff