PIC18F2320-I/SP Microchip Technology, PIC18F2320-I/SP Datasheet - Page 343

• Manufacturer Part Number: PIC18F2320-I/SP
• Description: IC MCU FLASH 4KX16 EEPROM 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2320-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI/I2C/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 26-19: I
© 2007 Microchip Technology Inc.
100
101
102
103
90
91
106
107
92
109
110
D102
Note 1:
Param.
No.
2:
T
T
T
T
T
T
T
T
T
T
T
C
Symbol
SU
SU
SU
AA
R
HIGH
LOW
F
HD
HD
BUF
B
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A fast mode I
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line,
T
is released.
:
:
:
:
:
STA
DAT
STO
R
STA
DAT
max. + T
Clock High Time
Clock Low Time
SDA and SCL Rise
Time
SDA and SCL Fall
Time
Start Condition Setup
Time
Start Condition Hold
Time
Data Input Hold Time 100 kHz mode
Data Input Setup
Time
Stop Condition Setup
Time
Output Valid from
Clock
Bus Free Time
Bus Capacitive Loading
2
C™ BUS DATA REQUIREMENTS (SLAVE MODE)
SU
2
:
C bus device can be used in a standard mode I
DAT
Characteristic
= 1000 + 250 = 1250 ns (according to the standard mode I
100 kHz mode
400 kHz mode
MSSP module
100 kHz mode
400 kHz mode
MSSP module
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
PIC18F2220/2320/4220/4320
20 + 0.1 C
20 + 0.1 C
1.5 T
1.5 T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
CY
CY
B
B
2
C bus system but the requirement, T
1000
3500
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
μs
μs
μs
μs
ns
ns
ns
ns
μs
μs
μs
μs
ns
μs
ns
ns
μs
μs
ns
ns
μs
μs
pF
2
C bus specification), before the SCL line
PIC18FXX20 must operate at a
minimum of 1.5 MHz
PIC18FXX20 must operate at a
minimum of 10 MHz
PIC18FXX20 must operate at a
minimum of 1.5 MHz
PIC18FXX20 must operate at a
minimum of 10 MHz
C
C
Only relevant for Repeated
Start condition
After this period, the first clock pulse is
generated
(Note 2)
(Note 1)
Time the bus must be free before a
new transmission can start
B
B
is specified to be from 10 to 400 pF
is specified to be from 10 to 400 pF
Conditions
DS39599G-page 341
SU
:
DAT
≥ 250 ns,