ATMEGA16L-8PU Atmel, ATMEGA16L-8PU Datasheet - Page 230
![IC AVR MCU 16K 8MHZ 3V 40DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA16L-8PU
Manufacturer Part Number
ATMEGA16L-8PU
Description
IC AVR MCU 16K 8MHZ 3V 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA16L-8MI.pdf
(26 pages)
2.ATMEGA16L-8MI.pdf
(357 pages)
3.ATMEGA16-16PU.pdf
(358 pages)
Specifications of ATMEGA16L-8PU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
JTAG/SPI/UART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
A/d Inputs
8-Channel, 10-Bit
Cpu Speed
8 MIPS
Eeprom Memory
512 Bytes
Input Output
32
Interface
JTAG/SPI/UART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
16K Bytes
Timers
2-8-bit, 1-16-bit
Voltage, Range
2.7-5.5 V
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 230 of 358
- Download datasheet (6Mb)
Boundary-scan Chain
Boundary-scan
Specific JTAG
Instructions
EXTEST; $0
IDCODE; $1
SAMPLE_PRELOAD;
$2
230
ATmega16(L)
Figure 115. Reset Register
The Boundary-scan Chain has the capability of driving and observing the logic levels on the dig-
ital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
Off-chip connections.
See
The instruction register is 4-bit wide, supporting up to 16 instructions. Listed below are the JTAG
instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction is not
implemented, but all outputs with tri-state capability can be set in high-impedant state by using
the AVR_RESET instruction, since the initial state for all port pins is tri-state.
As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which Data Register is selected as path between TDI and TDO for each instruction.
Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing
circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output
Data, and Input Data are all accessible in the scan chain. For Analog circuits having Off-chip
connections, the interface between the analog and the digital logic is in the scan chain. The con-
tents of the latched outputs of the Boundary-scan chain is driven out as soon as the JTAG IR-
register is loaded with the EXTEST instruction.
The active states are:
•
•
•
Optional JTAG instruction selecting the 32-bit ID-register as Data Register. The ID-register con-
sists of a version number, a device number and the manufacturer code chosen by JEDEC. This
is the default instruction after power-up.
The active states are:
•
•
Mandatory JTAG instruction for pre-loading the output latches and talking a snap-shot of the
input/output pins without affecting the system operation. However, the output latches are not
connected to the pins. The Boundary-scan Chain is selected as Data Register.
Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
Shift-DR: The Internal Scan Chain is shifted by the TCK input.
Update-DR: Data from the scan chain is applied to output pins.
Capture-DR: Data in the IDCODE-register is sampled into the Boundary-scan Chain.
Shift-DR: The IDCODE scan chain is shifted by the TCK input.
“Boundary-scan Chain” on page 232
External Reset Sources
From other Internal and
From
ClockDR · AVR_RESET
TDI
D
for a complete description.
Q
TDO
To
Internal Reset
2466R–AVR–06/08
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