AT91SAM7S32B-MU Atmel, AT91SAM7S32B-MU Datasheet - Page 505

• Manufacturer Part Number: AT91SAM7S32B-MU
• Description: IC MCU ARM7 32KB FLASH 48-VQFN
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S32B-MU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 35-5. Setup Transaction Followed by a Data OUT Transaction
35.5.2.2
35.5.2.3
6175K–ATARM–30-Aug-10
USB
Bus Packets
RXSETUP Flag
RX_Data_BKO
(UDP_CSRx)
FIFO (DPR)
Content
Data IN Transaction
Using Endpoints Without Ping-pong Attributes
Setup
PID
Setup Received
Data IN transactions are used in control, isochronous, bulk and interrupt transfers and conduct
the transfer of data from the device to the host. Data IN transactions in isochronous transfer
must be done using endpoints with ping-pong attributes.
To perform a Data IN transaction using a non ping-pong endpoint:
After the last packet has been sent, the application must clear TXCOMP once this has been set.
TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN
packet. An interrupt is pending while TXCOMP is set.
Warning: TX_COMP must be cleared after TX_PKTRDY has been set.
Note:
XX
1. The application checks if it is possible to write in the FIFO by polling TXPKTRDY in the
2. The application writes the first packet of data to be sent in the endpoint’s FIFO, writing
3. The application notifies the USB peripheral it has finished by setting the TXPKTRDY in
4. The application is notified that the endpoint’s FIFO has been released by the USB
5. The microcontroller writes the second packet of data to be sent in the endpoint’s FIFO,
6. The microcontroller notifies the USB peripheral it has finished by setting the TXPK-
7. The application clears the TXCOMP in the endpoint’s UDP_ CSRx.
Data Setup
endpoint’s UDP_ CSRx register (TXPKTRDY must be cleared).
zero or more byte values in the endpoint’s UDP_ FDRx register,
the endpoint’s UDP_ CSRx register.
device when TXCOMP in the endpoint’s UDP_ CSRx register has been set. Then an
interrupt for the corresponding endpoint is pending while TXCOMP is set.
writing zero or more byte values in the endpoint’s UDP_ FDRx register,
TRDY in the endpoint’s UDP_ CSRx register.
Refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more information on the
Data IN protocol layer.
Set by USB Device
ACK
PID
Setup Handled by Firmware
Data OUT
PID
Interrupt Pending
Data Setup
AT91SAM7S Series Preliminary
Data OUT
Cleared by Firmware
NAK
PID
Data OUT
PID
Data Out Received
Set by USB
Device Peripheral
XX
Data OUT
ACK
PID
Data
OUT
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