PIC18F2331-I/SP Microchip Technology, PIC18F2331-I/SP Datasheet
PIC18F2331-I/SP
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PIC18F2331-I/SP Summary of contents
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... PIC18F2331/2431/4331/4431 High Performance PWM and A/D 2003 Microchip Technology Inc. Data Sheet 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, Preliminary DS39616B ...
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... Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for ...
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... PIC18F4331 8192 4096 PIC18F4431 16384 8192 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Power-Managed Modes: • Run • Idle • Sleep • Idle mode currents down to 5.8 A typical • Sleep current down to 0.1 A typical • Timer1 oscillator, 1.8 A typical, 32 kHz, 2V • Watchdog Timer (WDT), 2.1 A typical • ...
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... PIC18F2331/2431/4331/4431 Pin Diagrams 28-Pin SDIP, SOIC MCLR/V /RE3 PP RA0/AN0 RA1/AN1 RA2/AN2/V -/CAP1/INDX REF RA3/AN3/V +/CAP2/QEA REF RA4/AN4/CAP3/QEB AV AV OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2/FLTA RC2/CCP1/FLTB RC3/T0CKI/T5CKI/INT0 Note 1: Low-voltage programming must be enabled. 40-Pin PDIP MCLR/V /RE3 PP RA0/AN0 RA1/AN1 RA2/AN2/V -/CAP1/INDX REF RA3/AN3/V +/CAP2/QEA REF ...
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... Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: Low-voltage programming must be enabled. 3: RD4 is the alternate pin for FLTA. 4: RD5 is the alternate pin for PWM4. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 RC0/T1OSO/T1CKI 32 ...
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... PIC18F2331/2431/4331/4431 Pin Diagrams (Continued) 44-Pin QFN (1) RC7/RX/DT/SDO (3) RD4/FLTA (4) RD5/PWM4 RD6/PWM6 RD7/PWM7 RB0/PWM0 RB1/PWM1 RB2/PWM2 Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: Low-voltage programming must be enabled. 3: RD4 is the alternate pin for FLTA. ...
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... Appendix E: Migration from Mid-range to Enhanced Devices ........................................................................................................... 381 Appendix F: Migration from High-end to Enhanced Devices ............................................................................................................. 381 INDEX ................................................................................................................................................................................................ 383 On-Line Support................................................................................................................................................................................. 391 Systems Information and Upgrade Hot Line ...................................................................................................................................... 391 Reader Response .............................................................................................................................................................................. 392 PIC18F2331/2431/4331/4431 Product Identification System ............................................................................................................ 393 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Preliminary DS39616B-page 5 ...
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... PIC18F2331/2431/4331/4431 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...
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... MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F2331/2431/4331/4431 family offer nine different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four crystal modes, using crystals or ceramic resonators. • ...
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... PIC18F2331/2431/4331/4431 1.2 Other Special Features • Memory Endurance: The enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 100 years. • ...
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... Details on Individual Family Members Devices in the PIC18F2331/2431/4331/4431 family are available in 28-pin (PIC18F2X31) and 40/44-pin (PIC18F4X31) packages. The block diagram for the two groups is shown in Figure 1-1. TABLE 1-1: DEVICE FEATURES Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) ...
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... PIC18F2331/2431/4331/4431 FIGURE 1-1: PIC18F2331/2431 BLOCK DIAGRAM Table Pointer<21> 21 inc/dec logic PCLATU Address Latch Program Memory PCU Program Counter Data Latch 16 TABLELATCH 8 ROMLATCH Instruction Decode & Control Power-up OSC2/CLKO Timing OSC1/CLKI Oscillator Generation Start-up Timer T1OSI Power-on T1OSO 4X PLL Watchdog Precision Brown-out ...
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... RD4 is the alternate pin for FLTA. 3: RC3, RC4 and RC5 are alternate pins for T0CKI/T5CKI, SDI/SDA, SCK/SCL respectively. 4: RD5 is the alternate pin for PWM4. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Data Bus<8> Data Latch 8 8 Data RAM (768 bytes) Address Latch ...
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... PIC18F2331/2431/4331/4431 TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS Pin Number Pin Name DIP SOIC MCLR/V /RE3 1 PP MCLR V PP RE3 OSC1/CLKI/RA7 9 OSC1 CLKI RA7 OSC2/CLKO/RA6 10 OSC2 CLKO RA6 RA0/AN0 2 RA0 AN0 RA1/AN1 3 RA1 AN1 RA2/AN2/V -/CAP1/INDX 4 REF RA2 AN2 V - REF CAP1 INDX ...
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... TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name DIP SOIC RB0/PWM0 21 RB0 PWM0 RB1/PWM1 22 RB1 PWM1 RB2/PWM2 23 RB2 PWM2 RB3/PWM3 24 RB3 PWM3 RB4/KBI0/PWM5 25 RB4 KBI0 PWM5 RB5/KBI1/PWM4/PGM 26 RB5 KBI1 PWM4 PGM RB6/KBI2/PGC 27 RB6 KBI2 PGC RB7/KBI3/PGD 28 RB7 KBI3 ...
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... PIC18F2331/2431/4331/4431 TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name DIP SOIC RC0/T1OSO/T1CKI 11 RC0 T1OSO T1CKI RC1/T1OSI/CCP2/FLTA 12 RC1 T1OSI CCP2 FLTA RC2/CCP1/FLTB 13 RC2 CCP1 FLTB RC3/T0CKI/T5CKI/INT0 14 RC3 T0CKI T5CKI INT0 RC4/INT1/SDI/SDA 15 RC4 INT1 SDI SDA RC5/INT2/SCK/SCL 16 RC5 INT2 SCK ...
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... LVDIN Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-Drain (no diode to V 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type 18 Master Clear (input) or programming voltage (input Master Clear (Reset) input. This pin is an active-low. Reset to the device. ...
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... PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name DIP TQFP QFN RB0/PWM0 33 8 RB0 PWM0 RB1/PWM1 34 9 RB1 PWM1 RB2/PWM2 35 10 RB2 PWM2 RB3/PWM3 36 11 RB3 PWM3 RB4/KBI0/PWM5 37 14 RB4 KBI0 PWM5 RB5/KBI1/PWM4 PGM RB5 KBI1 PWM4 ...
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... RC7 RX DT SDO Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-Drain (no diode to V 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type PORTC is a bidirectional I/O port. 34 I/O ST Digital I/O. O — Timer1 oscillator output Timer1 external clock input ...
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... PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name DIP TQFP QFN RD0/T0CKI/T5CKI 19 38 RD0 T0CKI T5CKI RD1/SDO 20 39 RD1 SDO RD2/SDI/SDA 21 40 RD2 SDI SDA RD3/SCK/SCL 22 41 RD3 SCK SCL RD4/FLTA 27 2 RD4 FLTA RD5/PWM4 28 3 RD5 ...
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... NC — 12, 13, 33, 34 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-Drain (no diode to V 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type PORTE is a bidirectional I/O port. 25 I/O ST Digital I/O. I Analog Analog input 6. 26 I/O ST Digital I/O ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 20 Preliminary 2003 Microchip Technology Inc. ...
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... OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types The PIC18F2331/2431/4331/4431 devices can be operated in 10 different oscillator modes. The user can program the configuration bits F 3:F OSC uration register 1H to select one of these 10 modes Low-power Crystal 2. XT Crystal/Resonator 3. HS High-speed Crystal/Resonator 4. HSPLL High-speed Crystal/Resonator with PLL enabled 5 ...
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... PIC18F2331/2431/4331/4431 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Typical Capacitor Values Crystal Tested: Osc Type Freq kHz 33 pF 200 kHz MHz MHz MHz MHz MHz 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation ...
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... Clock from Ext. System PIC18FXXXX RA6 I/O (OSC2) 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 2.5 RC Oscillator For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (R values and the operating temperature ...
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... PIC18F2331/2431/4331/4431 2.6 Internal Oscillator Block The PIC18F2331/2431/4331/4431 devices include an internal oscillator block, which generates two different clock signals; either can be used as the system’s clock source. This can eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC MHz clock source, which can be used to directly drive the system clock ...
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... Center frequency. Oscillator module is running at the calibrated frequency. 111111 • • 100000 = Minimum frequency Legend Readable bit -n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 R/W-0 R/W-0 R/W-0 — TUN5 TUN4 TUN3 • • • • ...
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... In addition to being a primary clock source, the internal oscillator block is available as a power-managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F2331/2431/4331/ 4431 devices are shown in Figure 2-8 ...
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... FIGURE 2-8: PIC18F2331/2431/4331/4431 CLOCK DIAGRAM Primary Oscillator OSC2 Sleep OSC1 Secondary Oscillator T1OSO T1OSCEN Enable Oscillator T1OSI OSCCON<6:4> Internal Oscillator Block INTRC Source 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 C4NFIG1H <3:0> HSPLL 4 x PLL LP, XT, HS, RC, EC Clock Source Option for Other Modules OSCCON< ...
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... R = Readable bit - n = Value at POR 2.7.2 OSCILLATOR TRANSITIONS The PIC18F2331/2431/4331/4431 devices contain circuitry to prevent clocking “glitches” when switching between clock sources. A short pause in the system clock occurs during the clock switch. The length of this pause is between 8 and 9 clock periods of the new clock source ...
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... EC LP, XT, and HS Note: See Table 4-1 in the Section 4.0 “Reset”, for time-outs due to Sleep and MCLR Reset. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 2.9 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 30 Preliminary 2003 Microchip Technology Inc. ...
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... Sleep mode offered by all ® PICmicro devices (where all system clocks are stopped) are both offered in the PIC18F2331/2431/ 4331/4431 devices (SEC_RUN and Sleep modes, respectively). However, additional power-managed modes are available that allow the user greater flexibil- ity in determining what portions of the device are oper- ating. The power-managed modes are event driven ...
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... PIC18F2331/2431/4331/4431 3.1.2 ENTERING POWER-MANAGED MODES In general, entry, exit and switching between power- managed clock sources requires clock source switch- ing. In each case, the sequence of events is the same. Any change in the power-managed mode begins with loading the OSCCON register and executing a SLEEP instruction. The SCS1:SCS0 bits select one of three power-managed clock sources ...
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... Not clocked (not running) Wake-up Any run mode Secondary, or INTOSC multiplexer 3.2 Sleep Mode The power-managed Sleep mode in the PIC18F2331/ 2431/4331/4431 devices is identical to that offered in ® all other PICmicro controllers entered by clearing the IDLEN and SCS1:SCS0 bits (this is the Reset state), and executing the SLEEP instruction. This shuts down the primary oscillator and the OSTS bit is cleared (see Figure 3-1) ...
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... PIC18F2331/2431/4331/4431 FIGURE 3-1: TIMING TRANSITION FOR ENTRY TO SLEEP MODE OSC1 CPU Clock Peripheral Clock Sleep Program PC Counter FIGURE 3-2: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) OSC1 (1) T OST PLL Clock Output CPU Clock Peripheral Clock Program PC Counter Wake Event Note 1024 T ...
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... Program PC Counter Wake Event 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 When a wake event occurs, the CPU is clocked from the primary clock source. A delay of approximately required between the wake event and when code exe- cution starts. This is required to allow the CPU to become ready to execute instructions. After the wake- up, the OSTS bit remains set ...
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... PIC18F2331/2431/4331/4431 3.3.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled, but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered by setting the Idle bit, modifying to SCS1:SCS0 = 01, and executing a SLEEP instruction. When the clock source is switched (see Figure 3-5) to the Timer1 oscillator, the primary oscilla- tor is shut down, the OSTS bit is cleared and the T1RUN bit is set ...
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... OST OSC PLL 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 was executed, and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source ...
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... PIC18F2331/2431/4331/4431 3.4 Run Modes If the IDLEN bit is clear when a SLEEP instruction is executed, the CPU and peripherals are both clocked from the source selected using the SCS1:SCS0 bits. While these operating modes may not afford the power conservation of Idle or Sleep modes, they do allow the device to continue executing instructions by using a lower frequency clock source ...
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... CPU Clock Peripheral Clock Program PC Counter 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Note: Caution should be used when modifying a single IRCF bit possible to select a higher clock speed than is supported by the low V Improper device operation may result if the V If the IRCF bits are all clear, the INTOSC output is not enabled, and the IOFS bit will remain clear ...
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... PIC18F2331/2431/4331/4431 3.4.4 EXIT TO IDLE MODE An exit from a power-managed run mode to its corre- sponding idle mode is executed by setting the IDLEN bit and executing a SLEEP instruction. The CPU is halted at the beginning of the instruction following the SLEEP instruction. There are no changes to any of the clock source status bits (OSTS, IOFS, or T1RUN). ...
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... Execution continues during the INTOSC stabilization period. 5: Required delay when waking from Sleep and all idle modes. This delay runs concurrently with any other required delays (see Section 3.3 “Idle Modes”). 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Power- Clock Ready Managed Status bit ...
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... PIC18F2331/2431/4331/4431 3.5.2 EXIT BY RESET Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock (defined in Configuration register 1H) becomes ready. At that time, the OSTS bit is set and the device begins executing code. Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 22.3 “ ...
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... If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast – decrement OSCTUNE. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 3.6.3 EXAMPLE MODE A CCP module can use free running Timer1, clocked by the internal oscillator block and an external event with a known period (i ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 44 Preliminary 2003 Microchip Technology Inc. ...
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... RESET The PIC18F2331/2431/4331/4431 devices differenti- ate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset Most registers are unaffected by a Reset ...
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... Electrostatic Discharge (ESD) or Electrical Overstress (EOS). 4.2 Power-up Timer (PWRT) The Power-up Timer (PWRT) of the PIC18F2331/2431/ 4331/4431 devices is an 11-bit counter, which uses the INTRC source as the clock input. This yields a count of 2048 65.6 ms. While the PWRT is counting, the device is held in Reset. ...
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... Legend unchanged unknown unimplemented bit, read as ‘0’. Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 (2) Power-up and Brown-out PWRTEN = 1 ...
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... PIC18F2331/2431/4331/4431 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices TOSU 2331 2431 4331 4431 TOSH 2331 2431 4331 4431 TOSL 2331 2431 4331 4431 STKPTR 2331 2431 4331 4431 PCLATU 2331 2431 4331 4431 PCLATH 2331 2431 4331 4431 ...
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... Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is disabled. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MCLR Resets Power-on Reset, WDT Reset ...
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... PIC18F2331/2431/4331/4431 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices ADRESH 2331 2431 4331 4431 ADRESL 2331 2431 4331 4431 ADCON0 2331 2431 4331 4431 ADCON1 2331 2431 4331 4431 ADCON2 2331 2431 4331 4431 CCPR1H 2331 2431 4331 4431 ...
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... Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is disabled. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MCLR Resets Power-on Reset, WDT Reset ...
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... PIC18F2331/2431/4331/4431 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices PTCON0 2331 2431 4331 4431 PTCON1 2331 2431 4331 4431 PTMRL 2331 2431 4331 4431 PTMRH 2331 2431 4331 4431 PTPERL 2331 2431 4331 4431 PTPERH 2331 2431 4331 4431 ...
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... Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is disabled. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MCLR Resets Power-on Reset, WDT Reset ...
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... PIC18F2331/2431/4331/4431 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
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... TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST max. First three stages of the PWRT timer. PLL 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 , V RISE > PWRT T OST T PWRT T OST T ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 56 Preliminary 2003 Microchip Technology Inc. ...
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... Accessing a location between the physically implemented memory and the 2-Mbyte address will cause a read of all ‘0’s (a NOP instruction). The PIC18F2331 and PIC18F4331 each have 8 Kbytes of Flash memory and can store up to 4,096 single-word instructions. The PIC18F2431 and PIC18F4431 each have 16 Kbytes of Flash memory and can store up to 8,192 single-word instructions ...
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... PIC18F2331/2431/4331/4431 5.2 Return Address Stack The return address stack allows any combination program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed interrupt is acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. ...
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... POP instruction. The POP instruc- tion discards the current TOS by decrementing the stack pointer. The previous value pushed onto the stack then becomes the TOS value. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 R/W-0 R/W-0 — SP4 ...
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... PIC18F2331/2431/4331/4431 5.3 Fast Register Stack A “fast return” option is available for interrupts. A fast register stack is provided for the Status, WREG and BSR registers and are only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt ...
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... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 5.6 Instruction Flow/Pipelining An “ ...
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... Instruction 3: MOVFF 5.7.1 TWO-WORD INSTRUCTIONS PIC18F2331/2431/4331/4431 devices have four two- word instructions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the 4 MSBs set to ‘1’s and is decoded as a NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction ...
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... Figure 5-6 shows the data memory organization for the PIC18F2331/2431/4331/4431 devices. The data memory map is divided into as many as 16 banks that contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR< ...
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... PIC18F2331/2431/4331/4431 FIGURE 5-6: DATA MEMORY MAP FOR PIC18F2331/2431/4331/4431 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 1110 Bank 14 00h = 1111 Bank 15 FFh DS39616B-page 64 Data Memory Map 000h Access RAM 05Fh 060h GPR ...
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... Table 5-1 and Table 5-2. The SFRs can be classified into two sets; those asso- ciated with the “core” function and those related to the peripheral functions. Those registers related to the TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2331/2431/4331/4431 DEVICES Address Name Address Name ...
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... PIC18F2331/2431/4331/4431 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) File Name Bit 7 Bit 6 Bit 5 TOSU — — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKPTR STKFUL STKUNF — PCLATU — — bit 21 PCLATH Holding register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — ...
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... TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 OSCCON IDLEN IRCF2 IRCF1 LVDCON — — IVRST WDTCON WDTW — — RCON IPEN — — TMR1H Timer1 register High Byte TMR1L Timer1 register Low Byte T1CON RD16 T1RUN ...
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... PIC18F2331/2431/4331/4431 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 EEADR EEPROM Address register EEDATA EEPROM Data register EECON2 EEPROM Control register2 (not a physical register) EECON1 EEPGD CFGS — — IPR3 — — — PIR3 — — — ...
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... TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 PTPERL PWM Time Base Period register (Lower 8 bits). PTPERH UNUSED PDC0L PWM Duty Cycle #0L register (Lower 8 bits) PDC0H UNUSED PDC1L PWM Duty Cycle #1L register (Lower 8 bits) PDC1H UNUSED PDC2L ...
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... PIC18F2331/2431/4331/4431 5.10 Access Bank The Access Bank is an architectural enhancement which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. This data memory region can be used for: • Intermediate computational values • Local variables of subroutines • ...
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... FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 If INDF0, INDF1 or INDF2 are read indirectly via a FSR, all ‘0’s are read (zero bit is set). Similarly, if INDF0, INDF1 or INDF2 are written to indirectly, the operation will be equivalent to a NOP instruction and the Status bits are not affected ...
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... PIC18F2331/2431/4331/4431 FIGURE 5-8: INDIRECT ADDRESSING OPERATION Instruction Executed Opcode BSR<3:0> Instruction Fetched Opcode FIGURE 5-9: INDIRECT ADDRESSING 3 11 Location Select Note 1: For register file map detail, see Table 5-1. DS39616B-page 72 0h RAM Address FFFh 12 File Address = access of an indirect addressing register ...
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... Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the Status register as 000u u1uu (where u = unchanged recommended, therefore, that only BCF, BSF, ...
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... PIC18F2331/2431/4331/4431 5.14 RCON Register The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device Reset. These flags include the TO, PD, POR, BOR and RI bits. This register is readable and writable. REGISTER 5-3: RCON REGISTER R/W-0 IPEN ...
Page 77
... Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The program memory space is 16-bits wide, while the data RAM space is 8-bits wide. Table reads and table writes move data between these two memory spaces DD through an 8-bit register (TABLAT) ...
Page 78
... PIC18F2331/2431/4331/4431 FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...
Page 79
... RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 Read completed Legend Readable bit W = Writable bit x = Bit is unknown 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 R/W-0 R/W-x — FREE WRERR S = Settable only U = Unimplemented bit, read as ‘ ...
Page 80
... PIC18F2331/2431/4331/4431 6.2.2 TABLAT TABLE LATCH REGISTER – The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR TABLE POINTER – REGISTER The Table Pointer (TBLPTR) addresses a byte within the program memory ...
Page 81
... TBLRD*+ MOVFW TABLAT MOVWF WORD_ODD 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT ...
Page 82
... PIC18F2331/2431/4331/4431 6.4 Erasing Flash Program Memory The minimum erase block size is 32 words or 64 bytes under firmware control. Only through the use of an external programmer, or through ICSP control can larger blocks of program memory be bulk erased. Word erase in Flash memory is not supported. ...
Page 83
... Disable interrupts. 9. Write 55h to EECON2. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation. All of the table write operations will essentially be short writes, because only the holding registers are written ...
Page 84
... PIC18F2331/2431/4331/4431 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64 MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ MOVFW TABLAT MOVWF POSTINC0 DECFSZ COUNTER GOTO READ_BLOCK ...
Page 85
... OSFIE — — Legend unknown unchanged reserved unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ; disable interrupts ; required sequence ; write 55H ; write AAH ; start program (CPU stall) ; re-enable interrupts ; loop until done ...
Page 86
... PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 84 Preliminary 2003 Microchip Technology Inc. ...
Page 87
... EEPROM memory. When clear, oper- ations will access the data EEPROM memory. When set, program memory is accessed. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Control bit CFGS determines if the access will be to the configuration registers or to program memory/data EEPROM memory. When set, subsequent operations range ...
Page 88
... PIC18F2331/2431/4331/4431 REGISTER 7-1: EECON1 REGISTER R/W-x R/W-x EEPGD CFGS bit 7 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access program Flash memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EE or Configuration Select bit 1 = Access configuration or calibration registers 0 = Access program Flash or data EEPROM memory bit 5 Unimplemented: Read as ‘ ...
Page 89
... SLEEP BCF EECON1, WREN 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruc- tion ...
Page 90
... PIC18F2331/2431/4331/4431 7.7 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in configuration words. External Read and Write opera- tions are disabled if either of these mechanisms are enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect configuration bit. Refer to Section 22.0 “ ...
Page 91
... X 8 HARDWARE MULTIPLIER 8.1 Introduction hardware multiplier is included in the ALU of the PIC18F2331/2431/4331/4431 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result. The result is stored into the 16-bit product register pair (PRODH:PRODL). The multiplier does not affect any flags in the Status register ...
Page 92
... PIC18F2331/2431/4331/4431 Example 8-3 shows the sequence unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0. EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L = (ARG1H ARG2H 2 (ARG1H ARG2L 2 (ARG1L ARG2H 2 (ARG1L ARG2L) EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE ...
Page 93
... Individual interrupts can be disabled through their corresponding enable bits. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 When the IPEN bit is cleared (default state), the inter- rupt priority feature is disabled and interrupts are com- devices have ...
Page 94
... PIC18F2331/2431/4331/4431 FIGURE 9-1: INTERRUPT LOGIC PSPIF PSPIE PSPIP ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation PSPIF PSPIE PSPIP ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts DS39616B-page 92 TMR0IF TMR0IE TMR0IP ...
Page 95
... Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt ...
Page 96
... PIC18F2331/2431/4331/4431 REGISTER 9-2: INTCON2 REGISTER R/W-1 R/W-1 RBPU INTEDG0 bit 7 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge ...
Page 97
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 R/W-0 R/W-0 — ...
Page 98
... PIC18F2331/2431/4331/4431 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Flag Registers (PIR1, PIR2). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 U-0 R/W-0 — ...
Page 99
... Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Not used in PWM mode Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 U-0 R/W-0 U-0 — — EEIF — Writable bit U = Unimplemented bit, read as ‘ ...
Page 100
... PIC18F2331/2431/4331/4431 REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT FLAG REGISTER 3 U-0 U-0 — — bit 7 bit 7-5 Unimplemented: Read as ‘0’ bit 4 PTIF: PWM Time Base Interrupt bit 1 = PWM Time Base matched the value in PTPER register. Interrupt is issued according to the postscaler settings. PTIF must be cleared in software. ...
Page 101
... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-0 R/W-0 ADIE RCIE TXIE SSPIE W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 102
... PIC18F2331/2431/4331/4431 REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 OSFIE bit 7 bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6-5 Unimplemented: Read as ‘0’ bit 4 EEIE: Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 Unimplemented: Read as ‘0’ bit 2 LVDIE: Low-Voltage Detect Interrupt Enable bit ...
Page 103
... IC1 interrupt disabled bit 0 TMR5IE: Timer5 Interrupt Enable bit 1 = Timer5 interrupt enabled 0 = Timer5 interrupt disabled Legend Readable bit -n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 R/W-0 R/W-0 — PTIE IC3DRIE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = bit is set ‘ ...
Page 104
... PIC18F2331/2431/4331/4431 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two peripheral interrupt priority registers (IPR1, IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
Page 105
... Unimplemented: Read as ‘0’ bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 U-0 R/W-1 U-0 — — EEIP — Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 106
... PIC18F2331/2431/4331/4431 REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 bit 7 bit 7-5 Unimplemented: Read as ‘0’ bit 4 PTIP: PWM Time Base Interrupt Priority bit 1 = High Priority 0 = Low Priority bit 3 IC3DRIP: IC3 Interrupt Priority/Direction Change Interrupt Priority bit IC3 Enabled (CAP3CON<3:0> IC3 Interrupt High Priority 0 = IC3 Interrupt Low Priority QEI Enabled (QEIM< ...
Page 107
... POR: Power-on Reset Status bit For details of bit operation, see Register 5-3 bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-3 Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 U-0 R/W-1 R-1 — — Writable bit U = Unimplemented bit, read as ‘ ...
Page 108
... PIC18F2331/2431/4331/4431 9.6 INTn Pin Interrupts External interrupts on the RC3/INT0, RC4/INT1 and RC5/INT2 pins are edge triggered: either rising, if the corresponding INTEDGx bit is set in the INTCON2 register, or falling, if the INTEDGx bit is clear. When a valid edge appears on the RC3/INT0 pin, the corresponding flag bit INTxF is set. This interrupt can be disabled by clearing the corresponding enable bit INTxE ...
Page 109
... PORT Note 1: I/O pins have diode protection to V 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 10.1 PORTA, TRISA and LATA Registers PORTA is a 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
Page 110
... PIC18F2331/2431/4331/4431 FIGURE 10-2: BLOCK DIAGRAM OF RA0 RD LATA Data Bus LATA PORTA Data Latch TRISA Q CK Analog Input TRIS Latch Mode RD TRISA PORTA To A/D Converter FIGURE 10-4: BLOCK DIAGRAM OF RA3:RA2 PINS RD LATA Data Bus D WR LATA CK or PORTA Data Latch D WR TRISA ...
Page 111
... FIGURE 10-5: BLOCK DIAGRAM OF RA4 Data Bus WR LATA or PORTA WR TRISA Note 1: Open-drain usually available on RA4 has been removed for this device. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 RD LATA Data Latch Analog TRIS Latch Input Mode RD TRISA PORTA To A/D Converter To CAP3/QEB Preliminary ...
Page 112
... PIC18F2331/2431/4331/4431 FIGURE 10-6: BLOCK DIAGRAM OF RA5 RD LATA Data Bus LATA PORTA Data Latch TRISA Analog TRIS Latch Input Mode or LVDIN Enabled RD TRISA PORTA To A/D Converter/LVD Module Input FIGURE 10-7: BLOCK DIAGRAM OF RA6 ECRA6 or RCRA6 Enable Data Bus RD LATA LATA PORTA Data Latch ...
Page 113
... RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 2: ANS5 through ANS8 are available only on the PIC18F4X31 devices. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Buffer TTL Input/output or analog input. TTL Input/output or analog input ...
Page 114
... PIC18F2331/2431/4331/4431 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
Page 115
... PWM0,1,2, 3 Data Data Bus D WR LATB CK or PORTB Data Latch D WR TRISB CK TRIS Latch RD PORTB Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 LATC TRISB Preliminary V DD ...
Page 116
... PIC18F2331/2431/4331/4431 FIGURE 10-10: BLOCK DIAGRAM OF RB4 (1) RBPU PORT/PWM Select PWM5 Data Data Bus D WR LATB CK or PORTB Data Latch D WR TRISB CK TRIS Latch RD TRISB RD LATB RD PORTB Set RBIF From other RB7:RB4 pins Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). ...
Page 117
... PWM4 Data Data Bus PORT Q CK Data Latch TRIS CK TRIS Latch RD TRIS RD PORT Set RBIF From other RB7:RB4 pins LVP Configuration Bit 1 = Low V Prog Enable 0 = only HV Prog 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 RBPU TTL Input Buffer Port EN Q3 Enable ICSP ...
Page 118
... PIC18F2331/2431/4331/4431 FIGURE 10-12: BLOCK DIAGRAM OF RB7:RB6 PINS Enable Debug or ICSP (1) RBPU RD LATB Data Bus LATB PORTB Data Latch TRISB CK Q TRIS Latch RD TRISC RD PORTB Enable Debug or ICSP Set RBIF From other RB7:RB4 pins (2) (3) PGC /PGD Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). ...
Page 119
... INTCON3 INT2IP INT1IP — Legend unknown unchanged value depends on condition. Shaded cells are not used by PORTB. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Function (1) Input/output pin, or PCPWM output PWM0. Internal software programmable weak pull-up. (1) Input/output pin, or PCPWM output PWM1. Internal software programmable weak pull-up. ...
Page 120
... PIC18F2331/2431/4331/4431 10.3 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i ...
Page 121
... Note 1: FLTA input is multiplexed with RC1 and RD4 using FLTAMX configuration bit in CONFIG3L register. FIGURE 10-15: BLOCK DIAGRAM OF RC2 PORT/CCP1 Select CCP1 Data Out Data Bus D WR LATC CK or PORTC Data Latch D WR TRISC CK TRIS Latch RD TRISC RD PORTC CCP1 Input/FLTB input 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 LATC LATC ...
Page 122
... PIC18F2331/2431/4331/4431 FIGURE 10-16: BLOCK DIAGRAM OF RC3 RD LATC Data Bus LATC PORTC Data Latch TRISC CK Q TRIS Latch RD TRISC RD PORTC T0CKI/T5CKI Input Note 1: The T0CKI/T5CKI bit is multiplexed with RD0 when the EXCLKM is enabled (= the configuration register. FIGURE 10-17: BLOCK DIAGRAM OF RC4 PORT/SSP Mode & SSPMX Select ...
Page 123
... Note 1: SCK/SCL are multiplexed on RD3 and RC5 using SSPMX bit in the configuration register. FIGURE 10-19: BLOCK DIAGRAM OF RC6 USART Select TX Data Out/CK Data Bus D WR LATC CK or PORTC Data Latch D WR TRISC CK TRIS Latch RD TRISC USART Select RD PORTC CK Input SS input 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Schmitt Trigger LATC ...
Page 124
... PIC18F2331/2431/4331/4431 FIGURE 10-20: BLOCK DIAGRAM OF RC6 (1) USART Select DT Data Out PORT/(SSPEN * SPI Mode ) Select (2) SDO Data Out RD LATC Data Bus LATC PORTC Data Latch TRISC CK Q TRIS Latch RD TRISC (1) USART Select RD PORTC RX/DT Data Input Note 1: USART is in Synchronous Master Transmission mode only (SYNC = 2: SDO must have its TRISC bit cleared in order to be able to drive RC7 ...
Page 125
... INT2IP INT1IP — Legend unknown unchanged 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Function Input/output port pin or Timer1 oscillator output/Timer1 clock input. Input/output port pin, Timer1 oscillator input, or Capture2 input/ Compare2 output/PWM output when CCP2MX configuration bit is disabled, or FLTA input. Input/output port pin, Capture1 input/Compare1 output/PWM1 output, or FLTB input ...
Page 126
... PIC18F2331/2431/4331/4431 10.4 PORTD, TRISD and LATD Registers Note: PORTD is only available on PIC18F4X31 devices. PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i ...
Page 127
... TRIS Latch RD TRISD RD PORTD FIGURE 10-23: BLOCK DIAGRAM OF RD4 RD LATD Data Bus LATD PORTD Data Latch TRISD CK Q TRIS Latch RD TRISD RD PORTD FLTA input Note 1: FLTAMX is located in the configuration register. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 LATD Schmitt Trigger Preliminary V DD ...
Page 128
... PIC18F2331/2431/4331/4431 FIGURE 10-24: BLOCK DIAGRAM OF RD3 2 I C™ Mode PORT/ SSPEN & SSPMX Select SCK/SCL Data Out RD LATD Data Bus LATD PORTD Data Latch TRISD CK Q TRIS Latch RD TRISD RD PORTC SCK or SCL input Note 1: SCK/SCL are multiplexed on RD3 and RC5 using SSPMX bit in the configuration register. ...
Page 129
... Note 1: The SDO output is multiplexed by SSPMX bit in the configuration register. FIGURE 10-27: BLOCK DIAGRAM OF RD0 RD LATD Data Bus LATD PORTD Data Latch TRISD Q CK TRIS Latch RD TRISD RD PORTD T0CKI/T5CKI Input Note 1: T0CKI/T5CKI are multiplexed by SSPMX bit in the configuration register. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Schmitt Trigger Schmitt Trigger Q D ...
Page 130
... PIC18F2331/2431/4331/4431 TABLE 10-7: PORTD FUNCTIONS Name Bit # Buffer Type RD0/T0CKI/T5CKI bit 0 ST RD1/SDO bit 1 ST RD2/SDI/SDA bit 2 ST RD3/SCK/SCL bit 3 ST RD4/FLTA bit 4 ST RD5/PWM4 bit 5 ST RD6/PWM6 bit 6 ST RD7/PWM7 bit 7 ST Legend Schmitt Trigger input, TTL = TTL input TABLE 10-8: ...
Page 131
... The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register read and write the latched output value for PORTE. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The fourth pin of PORTE (MCLR/V only pin. Its operation is controlled by the MCLRE con- figuration bit in (CONFIG3H< ...
Page 132
... PIC18F2331/2431/4331/4431 FIGURE 10-28: RE2:RE0 BLOCK DIAGRAM Data Bus D WR LATE CK or PORTE Data Latch D WR TRISE CK TRIS Latch RD TRISE RD PORTE To A/D Converter ch. AN6 or AN7 or AN8 FIGURE 10-29: RE3 BLOCK DIAGRAM MCLR/V MCLRE Data Bus Schmitt RD TRISE Trigger RD LATE Latch PORTE High Voltage Detect ...
Page 133
... TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 U-0 U-0 U-0 — — — — Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 134
... PIC18F2331/2431/4331/4431 TABLE 10-9: PORTE FUNCTIONS Name Bit # Buffer Type RE0/AN6 bit 0 ST RE1/AN7 bit 1 ST RE2/AN8 bit 2 ST MCLR/V /RE3 bit Legend Schmitt Trigger input, TTL = TTL input TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Name Bit 7 Bit 6 Bit 5 PORTE — ...
Page 135
... Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 11- readable and writable register that controls all the aspects of Timer0, including the prescale selection ...
Page 136
... PIC18F2331/2431/4331/4431 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE OSC T0CKI pin 1 T0SE T0CS Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale. FIGURE 11-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE F /4 OSC 0 T0CKI pin 1 Programmable Prescaler T0SE ...
Page 137
... Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA6 and RA7 are enabled as I/O pins depending on the Oscillator mode selected in Configuration Word 1H. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 11.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con- trol (i.e., it can be changed “ ...
Page 138
... PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 136 Preliminary 2003 Microchip Technology Inc. ...
Page 139
... Stops Timer1 Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Register 12-1 details the Timer1 control register. This register controls the Operating mode of the Timer1 module, and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit TMR1ON (T1CON< ...
Page 140
... PIC18F2331/2431/4331/4431 12.1 Timer1 Operation Timer1 can operate in one of these modes: • timer • synchronous counter • asynchronous counter The Operating mode is determined by the Clock Select bit, TMR1CS (T1CON<1>). FIGURE 12-1: TIMER1 BLOCK DIAGRAM TMR1IF Overflow TMR1 Interrupt Flag Bit TMR1H T1OSC ...
Page 141
... Microchip Technology Inc. PIC18F2331/2431/4331/4431 12.3 Timer1 Oscillator Layout Considerations The Timer1 oscillator for PIC18F2331/2431/4331/4431 devices incorporates an additional low-power feature. When this option is selected, it allows the oscillator to automatically reduce its power consumption when the microcontroller is in Sleep mode. During normal device operation, the oscillator draws full current ...
Page 142
... PIC18F2331/2431/4331/4431 12.4 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing Timer1 interrupt enable bit, TMR1IE (PIE1<0>). ...
Page 143
... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 u0uu uuuu Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ...
Page 144
... PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 142 Preliminary 2003 Microchip Technology Inc. ...
Page 145
... Prescaler Prescaler is 16 Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 13.1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device Reset ...
Page 146
... PIC18F2331/2431/4331/4431 13.2 Timer2 Interrupt The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 13-1: ...
Page 147
... Note 1: For Timer5 to operate during Sleep mode, T5SYNC must be set. Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Timer5 is a general-purpose timer/counter that incorpo- rates additional features for use with the Motion Feed- back module (see Section 16.0 “Motion Feedback Module”). It may also be used as a general-purpose timer or a special event trigger delay timer ...
Page 148
... PIC18F2331/2431/4331/4431 FIGURE 14-1: TIMER5 BLOCK DIAGRAM (16-BIT READ/WRITE MODE SHOWN) T5CKI Noise Filter F /4 OSC Internal Clock TMR5CS T5PS1:T5PS0 T5SYNC TMR5ON Special Event Trigger Input 1 from IC1 Timer5 Reset 0 (external) Set TMR5IF Special Event Trigger Output 14.1 Timer5 Operation Timer5 combines two 8-bit registers to function as a 16- bit timer. The TMR5L register is the actual low byte of the timer ...
Page 149
... Microchip Technology Inc. PIC18F2331/2431/4331/4431 Since the actual high byte of the Timer5 register pair is not directly readable or writable, it must be read and written to through the Timer5 High Byte Buffer register (TMR5H) ...
Page 150
... PIC18F2331/2431/4331/4431 14.5 Timer5 Interrupt Timer5 has the ability to generate an interrupt on a period match. When the PR5 register is loaded with a new period value (00FFh), the Timer5 time base incre- ments until its value is equal to the value of PR5. When a match occurs, the Timer5 interrupt is generated on the rising edge of Q4 ...
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... Timer5 Period Register Low Byte T5CON T5SEN RESEN T5MOD CAP1CON — CAP1REN — DFLTCON — FLT4EN FLT3EN Legend unknown unchanged, – = unimplemented. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE RBIE TMR0IF INT0IF PTIP IC3DRIP IC2QEIP IC1IP PTIE IC3DRIE IC2QEIE IC1IE PTIF ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 150 Preliminary 2003 Microchip Technology Inc. ...
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... Generate software interrupt-on-compare match (CCPxIF bit is set, CCP pin is unaffected) 1011 =Compare mode, Trigger special event (CCP2IF bit is set) 11xx =PWM mode Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 R/W-0 R/W-0 R/W-0 — DCxB1 DCxB0 ...
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... PIC18F2331/2431/4331/4431 15.1 CCP1 Module Capture/Compare/PWM Register 1 comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. TABLE 15-1: CCP MODE – TIMER RESOURCE CCP Mode Timer Resource Capture ...
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... CCP2 pin and Edge Detect Q’s 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 15.3.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit, CCP1IF, following any such change in operating mode ...
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... PIC18F2331/2431/4331/4431 15.4 Compare Mode In Compare mode, the 16-bit CCPR1 (CCPR2) register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/ CCP1 (RC1/CCP2) pin: • Is driven High • Is driven Low • Toggles output (High-to-Low or Low-to-High) • Remains unchanged (interrupt only) The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0) ...
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... PIE2 OSCFIE CMIE — IPR2 OSCFIP CMIP — Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE RBIE TMR0IF INT0IF TXIF SSPIF CCP1IF ...
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... PIC18F2331/2431/4331/4431 15.5 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level ...
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... DC2B1 Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 15.5.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1 ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 158 Preliminary 2003 Microchip Technology Inc. ...
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... Utilizes Input Capture 1 logic (IC1) • High and low velocity support 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Many of the features for the IC and QEI submodules are fully programmable, creating a flexible peripheral structure that can accommodate a wide range of in-system uses. An overview of the available features is presented in Table 16-1 ...
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... PIC18F2331/2431/4331/4431 FIGURE 16-1: MOTION FEEDBACK MODULE BLOCK DIAGRAM Special Reset Trigger Timer Reset Filter T5CKI Filter CAP3/QEB Filter CAP2/QEA Filter CAP1/INDX Clock T Divider CY CHGIF IC3IF QEIF IC2IF DS39616B-page 160 TMR5 Reset Control Timer5 Input Capture Logic TMR5<15:0> IC3 IC2 IC1 Postscaler ...
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... Note 1: CAP1BUF register is reconfigured as VELR register when QEI mode is active. 2: QEI generated velocity pulses, vel_out, are downsampled to produce this velocity capture signal. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Input channel (IC1) includes a special event trigger that can be configured for use in Velocity Measure- ment mode ...
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... PIC18F2331/2431/4331/4431 FIGURE 16-3: INPUT CAPTURE BLOCK DIAGRAM FOR IC2 AND IC3 CAP2/CAP3 Pin Prescaler Noise Filter 3 4 FLTCK<2:0> CAPxM<3:0> Note 1: IC2 and IC3 are denoted as x=2 and 3. 2: CAP2BUF is enabled as POSCNT when QEI mode is active. 3: CAP3BUF is enabled as MAXCNT when QEI mode is active. ...
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... For example, ‘CAPxREN’ may refer to the Capture Reset Enable bit in CAP1CON, CAP2CON or CAP3CON. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Registers U-0 R/W-0 R/W-0 — — ...
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... PIC18F2331/2431/4331/4431 Note 1: Input capture prescalers (cleared) when the Input Capture module is disabled (CAPxM = 0000). 2: When the Input Capture mode is changed without first disabling the module and entering the new Input Capture mode, a false interrupt (or special event trigger on IC1) may be generated. The user should ...
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... Pulse Width Measurement mode active on each rising edge detected. In the falling to rising Pulse Width Measure- ment mode active on each falling edge detected. 5: TMR5 Reset pulse is activated on the capture edge. CAP1REN bit has no bearing in this mode. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 of the CAPx input pin (CAPxM3:CAPxM0 = 0110 the rising to falling edge (CAPxM3:CAPxM0 = 0111). ...
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... PIC18F2331/2431/4331/4431 16.1.3.1 Pulse Width Measurement Timing Pulse width measurement accuracy can be only ensured when the pulse width high and low present on CAPx input exceeds one T clock cycle. The CY limitations depend on the mode selected: • When CAPxM3:CAPxM0 = 0110 (rising-to-falling edge delay), the CAPx input high pulse width (TccH) must exceed ...
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... The timer value is not affected when switch- ing into and out of various input capture modes. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.1.6 TIMER5 RESET Every Input Capture trigger can optionally reset (TMR5). Capture Reset Enable bit, CAPxREN, gates the automatic Reset of the time base of the capture event with this enable Reset signal ...
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... PIC18F2331/2431/4331/4431 FIGURE 16-7: CAPXIF INTERRUPTS AND IC1 SPECIAL EVENT TRIGGER OSC CAP1 pin IC1IF TMR5 Reset TMR5 XXXX (1) TMR5ON Note 1: Timer5 is only reset and enabled (assuming: TMR5ON = 0 and TMR5MOD = 1) when the Special Event Reset Trigger is enabled for the Timer5 Reset input. TMR5ON bit is asserted and Timer5 is reset on the Q1 rising edge following the event capture ...
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... Change Note 1: Timer5 may be reset on capture events only when CAPxRE = 1. 2: Trigger mode will not reset Timer5 unless RESEN = 0 in the T5CON register. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Reset Timer Timer on Capture (1) TMR5 optional Simple edge Capture mode (includes a ...
Page 172
... PIC18F2331/2431/4331/4431 16.2 Quadrature Encoder Interface The Quadrature Encoder Interface (QEI) decodes speed and motion sensor information. It can be used in any application that uses a quadrature encoder for feedback. The interface implements these features: • Three QEI inputs: two phase signals (QEA and QEB) and one index signal (INDX) • ...
Page 173
... ERROR bit must be cleared in software. Legend Readable bit -n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The operation of the QEI is controlled by the QEICON configuration register. See Register 16-2. Note: In the event that both QEI and IC are enabled, QEI will take precedence and IC will remain disabled ...
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... PIC18F2331/2431/4331/4431 16.2.2 QEI MODES Position measurement resolution depends on how often the Position Counter register, POSCNT, is incremented. There are two QEI update modes to measure the rotor’s position: QEI x2 and QEI x4. TABLE 16-4: QEI MODES QEIM2: Mode/ Description QEIM0 Reset (1) — QEI disabled ...
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... The value of the position counter is not affected during QEI mode changes, nor when the QEI is disabled altogether. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.2.4 QEI INTERRUPTS The position counter interrupt occurs, and the interrupt flag (IC2QEIF) is set, based on the following events: • ...
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... PIC18F2331/2431/4331/4431 FIGURE 16-9: QEI INPUTS WHEN SAMPLED BY THE FILTER (DIVIDE RATIO = 1: QEA pin QEB pin QEA input QEB input Note 1: The module design allows a quadrature frequency FIGURE 16-10: QEI MODULE RESET TIMING ON PERIOD MATCH QEA QEB + count (+/-) (1) POSCNT MAXCNT MAXCNT=1527 IC2QEIF ...
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... To optimize register space, the input capture channel one (IC1) is used to capture TMR5 counter values. Input capture buffer register, CAP1BUF, is redefined in Velocity Measurement mode, VELM = 0, as the Velocity Register buffer (VREGH, VREGL). 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Forward Reverse Note 2 Note ...
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... PIC18F2331/2431/4331/4431 16.2.6.1 Velocity Event Timing The event pulses are reduced by a fixed ratio by the velocity pulse divider. The divider is useful for high-speed measurements where the velocity events happen frequently. By producing a single output pulse for a given number of input event pulses, the counter can track larger pulse counts (i ...
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... The velocity event reduction ratio can be set with the PDEC1:PDEC0 control bits (QEICON<1:0>) to 1:4, 1:16, 1: reduction (1:1). The velocity postscaler settings are automatically reloaded from their previous values as the Velocity mode is re-enabled. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 (1) Forward 1537 Old Value 1529 Q1 ...
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... PIC18F2331/2431/4331/4431 16.3 Noise Filters The Motion Feedback module includes three noise rejection filters on CAP1/INDX, CAP2/QEA and CAP3/QEB. The filter block also includes a fourth filter for the T5CKI pin. They are intended to help reduce spurious noise spikes which may cause the input sig- nals to become corrupted at the inputs ...
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... Velocity register event IC2QEIF IC2 capture Position measurement event IC3DRIF IC3 capture Direction change event 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 (3) Noise glitch . CY 16.5 Operation in Sleep Mode 16.5.1 3X INPUT CAPTURE IN SLEEP MODE Since the input capture can operate only when its time base is configured in a Synchronous mode, the input capture will not capture any events ...
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... PIC18F2331/2431/4331/4431 TABLE 16-8: REGISTERS ASSOCIATED WITH THE MOTION FEEDBACK MODULE Name Bit 7 Bit 6 Bit 5 INTCON GIE/GIEH PEIE/GIEL TMR0IE IPR3 — — PIE3 — — PIR3 — — TMR5H Timer5 Register High Byte (Buffer) TMR5L Timer5 Register Low Byte PR5H Timer5 Period Register High Byte ...
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... Brushless DC (BLDC) Motors • Uninterruptible Power Supplies (UPS) • Multiple DC Brush Motors 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The PWM module has the following features: • eight PWM I/O pins with four duty cycle generators. Pins can be paired to get a complete half-bridge control ...
Page 184
... PIC18F2331/2431/4331/4431 FIGURE 17-1: POWER CONTROL PWM MODULE BLOCK DIAGRAM Internal Data Bus 8 PWMCON0 8 PWMCON1 8 DTCON 8 FLTCON 8 OVDCON<D/S> PTMR Comparator PTPER 8 PTPER Buffer 8 PTCON Comparator SEVTDIR 8 PTDIR SEVTCMP Note 1: Only PWM Generator #3 is shown in detail. The other generators are identical; their details are omitted for clarity. ...
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... In complimentary modes, the even PWM pins must always be the complement of the corresponding odd PWM pin. For example, PWM0 will be the complement of PWM1, PWM2 will be the complement of PWM3, and so on. The dead time 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 V DD Dead-Band Generator Note: ...
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... PIC18F2331/2431/4331/4431 17.1 Control Registers The operation of the PWM module is controlled by a total of 22 registers. Eight of these are used to configure the features of the module: • PWM Timer Control register 0 (PTCON0) • PWM Timer Control register 1 (PTCON1) • PWM Control register 0 (PWMCON0) • PWM Control register 1 (PWMCON1) • ...
Page 187
... The up/down counting modes produce center-aligned PWM generation. The Single-shot mode allows the PWM module to support pulse control of certain electronically commutated motors (ECMs) and produces edge-aligned operation. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PTMR Clock Timer RESET Up/Down Zero match Timer ...
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... PIC18F2331/2431/4331/4431 REGISTER 17-1: PTCON0: PWM TIMER CONTROL REGISTER 0 R/W-0 R/W-0 PTOPS3 PTOPS2 bit 7 bit 7-4 PTOPS3:PTOPS0: PWM Time Base Output Postscale Select bits 0000 =1:1 Postscale 0001 =1:2 Postscale . . . 1111 =1:16 Postscale bit 3-2 PTCKPS1:PTCKPS0: PWM Time Base Input Clock Prescale Select bits ...
Page 189
... PIC18F2X31 devices; PWM[7:0] outputs are enabled for PIC18F4X31devices. When PWMEN2:PWMEN0 = 111, PWM outputs 1, 3 and 5 are enabled in PIC18F2X31devices; PWM outputs and 7 are enabled in PIC18F4X31 devices. 3: Unimplemented in PIC18F2X31 devices; maintain these bits clear. Legend Readable bit -n = Value at POR 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 (1) (1) (1) R/W-1 R/W-1 R/W-0 (1) (2) ...
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... PIC18F2331/2431/4331/4431 REGISTER 17-4: PWMCON1: PWM CONTROL REGISTER 1 R/W-0 SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR bit 7 bit 7-4 SEVOPS3:SEVOPS0: PWM Special Event Trigger Output Postscale Select bits 0000 =1:1 Postscale 0001 =1:2 Postscale . . . 1111 =1:16 Postscale bit 3 SEVTDIR: Special Event Trigger Time Base Direction bit special event trigger will occur when the PWM time base is counting downwards ...
Page 191
... PTMR_INT_REQ PTIF bit Note 1: PWM Time Base Period register, PTPER, is loaded with the value FFFh for this example. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.4 PWM Time Base Interrupts The PWM timer can generate interrupts based on the modes of operation selected by PTMOD<1:0> bits and the postscaler bits (PTOPS< ...
Page 192
... PIC18F2331/2431/4331/4431 17.4.2 INTERRUPTS IN SINGLE-SHOT MODE When the PWM time base is in the Single-shot mode (PTMOD<1:0> = 01), an interrupt event is generated when a match with the PTPER register occurs. The PWM timer register (PTMR) is reset to zero on the following input clock edge, and the PTEN bit is cleared. ...
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... PWM TIME BASE INTERRUPTS, UP/DOWN COUNTING MODE PRESCALER = 1 OSC PTMR 002h PTDIR bit PTMR_INT_REQ 1 1 PTIF bit PRESCALER = 1 PTMR 002h PTDIR bit 1 1 PTMR_INT_REQ PTIF bit Note 1: Interrupt flag bit PTIF is sampled here (every Q1). 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 001h 000h 001h 000h 1 1 Preliminary ...
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... PIC18F2331/2431/4331/4431 17.4.4 INTERRUPTS IN DOUBLE UPDATE MODE This mode is available in Up/Down Counting mode. In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR register is equal to zero and each time the PTMR matches with PTPER register. Figure 17-8 shows the interrupts in Up/Down Counting mode with double updates ...
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... The PWM frequency is the inverse of period PWM frequency = ------------------------------ - PWM period 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined from the following formula: EQUATION 17-3: Resolution = The PWM resolutions and frequencies are shown for a selection of execution speeds and PTPER values in Table 17-2 ...
Page 196
... PIC18F2331/2431/4331/4431 FIGURE 17-9: PWM PERIOD BUFFER UPDATES IN FREE RUNNING COUNT MODE New PTPER value = 007 Old PTPER value = 004 1 0 FIGURE 17-10: PWM PERIOD BUFFER UPDATES IN UP/DOWN COUNTING MODES New PTPER value = 007 Old PTPER value = 004 DS39616B-page 194 Period value loaded from PTPER Buffer register ...
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... duty cycle match occurs on Q4 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The value in each Duty Cycle register determines the amount of time that the PWM output is in the active state. The upper 12 bits of PDCn hold the actual duty cycle value from PTMRH/L< ...
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... PIC18F2331/2431/4331/4431 17.6.2 DUTY CYCLE REGISTER BUFFERS The four PWM Duty Cycle double-buffered to allow glitchless updates of the PWM outputs. For each duty cycle block, there is a Duty Cycle Buffer register that is accessible by the user and a second Duty Cycle register that holds the actual compare value used in the present PWM period ...
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... Duty Cycle first PWM Period 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Duty cycle value loaded from buffer register New values written to duty cycle buffer. inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is equal to or greater than the value in the PTPER register ...
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... PIC18F2331/2431/4331/4431 17.6.5 COMPLEMENTARY PWM OPERATION The Complementary mode of PWM operation is useful to drive one or more power switches in half-bridge configuration as shown in Figure 17-16. This inverter topology is typical for a 3-phase induction motor, brushless DC motor or a 3-phase Uninterruptible Power Supply (UPS) control applications. Each upper/lower ...