PIC18F2331-I/SP Microchip Technology, PIC18F2331-I/SP Datasheet
PIC18F2331-I/SP
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... PIC18F2331/2431/4331/4431 Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D 2010 Microchip Technology Inc. Data Sheet 28/40/44-Pin Enhanced Flash DS39616D ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F4431 16384 8192 768 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Power-Managed Modes: • Run: CPU on, Peripherals on • Idle: CPU off, Peripherals on • Sleep: CPU off, Peripherals off • Ultra Low Input Leakage • Idle mode Currents Down to 5.8 A, Typical • ...
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... For the QFN package recommended that the bottom pad be connected to V Note 1: DS39616D-page -/CAP1/INDX 1 21 REF +/CAP2/QEA 2 20 REF 3 19 PIC18F2331 PIC18F2431 OSC1/CLKI/RA7 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PWM4/PGM RB4/KBI0/PWM5 RB3/PWM3 RB2/PWM2 RB1/PWM1 RB0/PWM0 RC7/RX/DT/SDO RC6/TX/CK/SS RC5/INT2/SCK/SCL RC4/INT1/SDI/SDA RB3/PWM3 RB2/PWM2 RB1/PWM1 RB0/PWM0 RC7/RX/DT/SDO . SS 2010 Microchip Technology Inc. ...
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... RD0/T0CKI/T5CKI RD1/SDO Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ...
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... PIC18F2331/2431/4331/4431 Pin Diagrams (Continued) 44-Pin TQFP RC7/RX/DT/SDO (2) RD4/FLTA (3) RD5/PWM4 RD6/PWM6 RD7/PWM7 RB0/PWM0 RB1/PWM1 RB2/PWM2 RB3/PWM3 Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4. ...
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... Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: For the QFN package recommended that the bottom pad be connected RD4 is the alternate pin for FLTA. 4: RD5 is the alternate pin for PWM4. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 OSC2/CLKO/RA6 1 33 OSC1/CLKI/RA7 2 ...
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... PIC18F2331/2431/4331/4431 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with PIC18F Microcontrollers ..................................................................................................... 25 3.0 Oscillator Configurations ............................................................................................................................................................ 29 4.0 Power-Managed Modes ............................................................................................................................................................. 39 5.0 Reset .......................................................................................................................................................................................... 47 6.0 Memory Organization ................................................................................................................................................................. 61 7.0 Data EEPROM Memory ............................................................................................................................................................. 79 8.0 Flash Program Memory .............................................................................................................................................................. 85 9 Hardware Multiplier............................................................................................................................................................ 95 10.0 Interrupts .................................................................................................................................................................................... 97 11.0 I/O Ports ................................................................................................................................................................................... 113 12 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 DS39616D-page 9 ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 10 2010 Microchip Technology Inc. ...
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... MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F2331/2431/4331/4431 family family offer nine different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four Crystal modes, using crystals or ceramic resonators. • ...
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... PIC18F2331/2431/4331/4431 1.2 Other Special Features • Memory Endurance: The enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 100 years. • ...
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... Like all Microchip PIC18 devices, members of the PIC18F2331/2431/4331/4431 family are available as both standard and low-voltage devices. Standard devices with Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F2331), Kbytes for accommodate an operating V Low-voltage parts, designated by “LF” (such as PIC18LF2331), function over an extended ...
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... PIC18F2331/2431/4331/4431 FIGURE 1-1: PIC18F2331/2431 (28-PIN) BLOCK DIAGRAM Table Pointer<21> 21 inc/dec logic PCLATU Address Latch Program PCU Memory Program Counter Data Latch 16 Table Latch 8 ROM Latch Instruction Decode & Control OSC2/CLKO Timing OSC1/CLKI Generation Start-up Timer T1OSI T1OSO 4x PLL Precision Band Gap ...
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... RD4 is the alternate pin for FLTA. 2: RC3, RC4 and RC5 are alternate pins for T0CKI/T5CKI, SDI/SDA, SCK/SCL, respectively. 3: RD5 is the alternate pin for PWM4. 4: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Data Bus<8> Data Latch 8 8 Data RAM (768 bytes) Address Latch ...
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... PIC18F2331/2431/4331/4431 TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS Pin Number Pin Name SPDIP, SOIC MCLR MCLR V PP OSC1/CLKI/RA7 9 OSC1 CLKI RA7 OSC2/CLKO/RA6 10 OSC2 CLKO RA6 RA0/AN0 2 RA0 AN0 RA1/AN1 3 RA1 AN1 RA2/AN2/V -/CAP1/INDX 4 REF RA2 AN2 V - REF CAP1 INDX RA3/AN3/V +/CAP2/QEA 5 REF ...
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... TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name SPDIP, SOIC RB0/PWM0 21 RB0 PWM0 RB1/PWM1 22 RB1 PWM1 RB2/PWM2 23 RB2 PWM2 RB3/PWM3 24 RB3 PWM3 RB4/KBI0/PWM5 25 RB4 KBI0 PWM5 RB5/KBI1/PWM4/PGM 26 RB5 KBI1 PWM4 PGM RB6/KBI2/PGC 27 RB6 KBI2 PGC RB7/KBI3/PGD 28 RB7 KBI3 ...
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... PIC18F2331/2431/4331/4431 TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name SPDIP, SOIC RC0/T1OSO/T1CKI 11 RC0 T1OSO T1CKI RC1/T1OSI/CCP2/FLTA 12 RC1 T1OSI CCP2 FLTA RC2/CCP1 13 RC2 CCP1 RC3/T0CKI/T5CKI/INT0 14 RC3 T0CKI T5CKI INT0 RC4/INT1/SDI/SDA 15 RC4 INT1 SDI SDA RC5/INT2/SCK/SCL 16 RC5 INT2 SCK SCL ...
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... RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin Note 1: for SCK/SCL; RC7 is the alternate pin for SDO. RD4 is the alternate pin for FLTA. 2: RD5 is the alternate pin for PWM4. 3: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type 18 Master Clear (input) or programming voltage (input Master Clear (Reset) input ...
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... PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP TQFP QFN RA0/AN0 2 19 RA0 AN0 RA1/AN1 3 20 RA1 AN1 RA2/AN2/V -/CAP1 REF INDX RA2 AN2 V - REF CAP1 INDX RA3/AN3 REF CAP2/QEA RA3 AN3 V + REF CAP2 QEA RA4/AN4/CAP3/QEB ...
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... SCK/SCL; RC7 is the alternate pin for SDO. RD4 is the alternate pin for FLTA. 2: RD5 is the alternate pin for PWM4. 3: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. ...
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... PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP TQFP QFN RC0/T1OSO/T1CKI 15 32 RC0 T1OSO T1CKI RC1/T1OSI/CCP2 FLTA RC1 T1OSI CCP2 FLTA RC2/CCP1/FLTB 17 36 RC2 CCP1 FLTB RC3/T0CKI/T5CKI INT0 RC3 (1) T0CKI (1) T5CKI INT0 RC4/INT1/SDI/SDA 23 42 RC4 INT1 ...
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... RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin Note 1: for SCK/SCL; RC7 is the alternate pin for SDO. RD4 is the alternate pin for FLTA. 2: RD5 is the alternate pin for PWM4. 3: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type PORTD is a bidirectional I/O port. 38 I/O ST Digital I/O ...
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... PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP TQFP QFN RE0/AN6 8 25 RE0 AN6 RE1/AN7 9 26 RE1 AN7 RE2/AN8 10 27 RE2 AN8 — 12, 13, 33, 34 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... GUIDELINES FOR GETTING STARTED WITH PIC18F MICROCONTROLLERS 2.1 Basic Connection Requirements Getting started with the PIC18F2331/2431/4331/4431 family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: • All V and V ...
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... PIC18F2331/2431/4331/4431 2.2 Power Supply Pins 2.2.1 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher ...
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... Overstress (EOS). Ensure that the MCLR pin V and V specifications are met 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 2.4 ICSP Pins device The PGC and PGD pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible ...
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... PIC18F2331/2431/4331/4431 2.5 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator Section 3.0 “Oscillator Configurations” The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0 ...
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... OSCILLATOR CONFIGURATIONS 3.1 Oscillator Types The PIC18F2331/2431/4331/4431 devices can be operated in 10 different oscillator modes. The user can program the Configuration bits, FOSC<3:0>, in Configuration Register 1H to select one of these 10 modes Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4. HSPLL High-Speed Crystal/Resonator with PLL Enabled 5 ...
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... PIC18F2331/2431/4331/4431 TABLE 3-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Typical Capacitor Values Crystal Tested: Osc Type Freq kHz 33 pF 200 kHz MHz MHz MHz MHz MHz 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation ...
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... Clock from Ext. System PIC18FXXXX RA6 I/O (OSC2) 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 3.5 RC Oscillator For timing-insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The actual oscillator frequency is a function of several factors: • Supply voltage • ...
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... PIC18F2331/2431/4331/4431 3.6 Internal Oscillator Block The PIC18F2331/2431/4331/4431 devices include an internal oscillator block, which generates two different clock signals; either can be used as the system’s clock source. This can eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC MHz clock source, which can be used to directly drive the system clock ...
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... If the internally clocked timer value is greater than expected, the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘ ...
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... Like previous PIC18 devices, the PIC18F2331/2431/ 4331/4431 devices include a feature that allows the sys- tem clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F2331/ 2431/4331/4431 devices offer two alternate clock sources. When enabled, these give additional options for switching to the various power-managed operating modes ...
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... FIGURE 3-8: PIC18F2331/2431/4331/4431 CLOCK DIAGRAM Primary Oscillator OSC2 Sleep OSC1 Secondary Oscillator T1OSO T1OSCEN Enable Oscillator T1OSI OSCCON<6:4> Internal Oscillator Block INTRC Source 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 CONFIG1H <3:0> HSPLL 4 x PLL LP, XT, HS, RC, EC Clock Source Option for other Modules OSCCON< ...
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... PIC18F2331/2431/4331/4431 REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IDLEN: Idle Enable bit 1 = Idle mode enabled; CPU core is not clocked in power-managed modes 0 = Run mode enabled; CPU core is clocked in power-managed modes bit 6-4 IRCF< ...
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... OSCILLATOR TRANSITIONS The PIC18F2331/2431/4331/4431 devices contain circuitry to prevent clocking “glitches” when switching between clock sources. A short pause in the system clock occurs during the clock switch. The length of this pause is between 8 and 9 clock periods of the new clock source. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 38 2010 Microchip Technology Inc. ...
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... POWER-MANAGED MODES PIC18F2331/2431/4331/4431 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power-managed modes: • Run modes • ...
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... PIC18F2331/2431/4331/4431 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • ...
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... PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 n-1 n (1) ...
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... PIC18F2331/2431/4331/4431 If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the device clocks. If the IRCF bits are changed from all clear (thus, ...
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... Sleep Mode The power-managed Sleep mode in the PIC18F2331/ 2431/4331/4431 devices is identical to the legacy Sleep mode offered in all other PIC devices entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator clock source status bits are cleared ...
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... PIC18F2331/2431/4331/4431 4.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “ ...
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... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON<7>) is set. Otherwise, code execution ...
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... PIC18F2331/2431/4331/4431 4.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode, where the primary clock source is not stopped; and • the primary clock source is not any of the LP, XT HSPLL modes ...
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... RESET The PIC18F2331/2431/4331/4431 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset FIGURE 5-1: ...
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... PIC18F2331/2431/4331/4431 5.1 RCON Register Device Reset events are tracked through the RCON register (Register 5-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be cleared by the event and must be set by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred ...
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... MCLR Reset path that detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, including the Watchdog Timer. In PIC18F2331/2431/4331/4431 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. For more information, see “ ...
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... Oscillator Start-up Timer (OST) • PLL Lock Time-out 5.5.1 POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) of PIC18F2331/2431/ 4331/4431 devices is an 11-bit counter that uses the INTRC source as the clock input. This yields an approximate time interval of 2,048 x 32 s = 65.6 ms. ...
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... MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Status bits from the RCON register (RI, TO, PD, POR and BOR) are set or cleared differently in different Reset situations, as indicated in are used in software to determine the nature of the Reset. ...
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... PIC18F2331/2431/4331/4431 FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39616D-page 52 T PWRT RISE > PWRT T OST ): CASE 2 ...
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... Interrupt exit from power-managed modes u = unchanged unknown unimplemented bit, read as ‘0’. Legend: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the Note 1: interrupt vector (0x000008h or 0x000018h). 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 T PWRT T OST T PLL ...
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... PIC18F2331/2431/4331/4431 TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices TOSU 2331 2431 4331 4431 TOSH 2331 2431 4331 4431 TOSL 2331 2431 4331 4431 STKPTR 2331 2431 4331 4431 PCLATU 2331 2431 4331 4431 PCLATH 2331 2431 4331 4431 ...
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... Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE 6: pin, they are disabled and read as ‘0’. The 28-pin devices do not have only RE3 implemented. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MCLR Resets Power-on Reset, WDT Reset ...
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... PIC18F2331/2431/4331/4431 TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices ADRESH 2331 2431 4331 4431 ADRESL 2331 2431 4331 4431 ADCON0 2331 2431 4331 4431 ADCON1 2331 2431 4331 4431 ADCON2 2331 2431 4331 4431 ADCON3 2331 2431 4331 4431 ...
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... Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE 6: pin, they are disabled and read as ‘0’. The 28-pin devices do not have only RE3 implemented. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MCLR Resets Power-on Reset, WDT Reset ...
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... PIC18F2331/2431/4331/4431 TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices PTCON0 2331 2431 4331 4431 PTCON1 2331 2431 4331 4431 PTMRL 2331 2431 4331 4431 PTMRH 2331 2431 4331 4431 PTPERL 2331 2431 4331 4431 PTPERH 2331 2431 4331 4431 ...
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... Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE 6: pin, they are disabled and read as ‘0’. The 28-pin devices do not have only RE3 implemented. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MCLR Resets Power-on Reset, WDT Reset ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 60 2010 Microchip Technology Inc. ...
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... Accessing a location between the upper bound- ary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction). The PIC18F2331/4331 devices each have 8 Kbytes of Flash memory and can store up to 4,096 single-word instructions. The PIC18F2431/4431 devices each have 16 Kbytes of Flash memory and can store up to 8,192 single-word instructions ...
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... PIC18F2331/2431/4331/4431 6.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The bits wide and contained in three 8-bit registers. The low byte, known as the PCL register, is both readable and writ- able. The high byte (PCH register) contains the PC< ...
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... SP<4:0>: Stack Pointer Location bits Bit 7 and bit 6 are cleared by user software POR. Note 1: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Returning a value of zero to the Note: underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken ...
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... PIC18F2331/2431/4331/4431 6.1.2.3 PUSH and POP Instructions Since the Top-of-Stack (TOS) is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execu- tion is a desirable option. To push the current PC value onto the stack, a PUSH instruction can be executed. ...
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... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 6.2 Clocking Scheme/Instruction ...
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... PIC18F2331/2431/4331/4431 6.4 Instructions in Program Memory The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). Figure 6-5 shows an example of how instruction words are stored in the program memory. ...
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... GPRs are used for data storage and scratchpad operations in the user’s application. Any read of an unimplemented location will read as ‘0’s. FIGURE 6-6: DATA MEMORY MAP FOR PIC18F2331/2431/4331/4431 DEVICES Data Memory Map BSR<3:0> 00h = 0000 ...
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... PIC18F2331/2431/4331/4431 6.5.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accom- plished with a RAM banking scheme ...
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... Table 6-2. The SFRs can be classified into two sets: those asso- ciated with the “core” function and those related to the peripheral functions. Those registers related to the TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2331/2431/4331/4431 DEVICES Address Name Address FFFh TOSU ...
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... Bit 21 of the PC is only available in Test mode and Serial Programming modes. 3: These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’. 4: The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3 5: reads ‘ ...
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... Bit 21 of the PC is only available in Test mode and Serial Programming modes. 3: These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’. 4: The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3 5: reads ‘ ...
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... Bit 21 of the PC is only available in Test mode and Serial Programming modes. 3: These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’. 4: The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3 5: reads ‘ ...
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... Bit 21 of the PC is only available in Test mode and Serial Programming modes. 3: These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’. 4: The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3 5: reads ‘ ...
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... PIC18F2331/2431/4331/4431 6.6 STATUS Register The STATUS register, shown in Register the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic ...
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... Access Bank. Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their op codes. In these cases, the BSR is ignored entirely. ...
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... PIC18F2331/2431/4331/4431 6.7.3.1 FSR Registers and the INDF Operand At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion ...
Page 77
... INDF0 as an operand will return 00h. Attempts to write to INDF1 using INDF0 as the operand will result in a NOP. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing ...
Page 78
... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 78 2010 Microchip Technology Inc. ...
Page 79
... EEADR The Address register can address 256 bytes of data EEPROM. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 7.2 EECON1 and EECON2 Registers Access to the data EEPROM is controlled by two registers: EECON1 and EECON2. These are the same range. The data registers which control access to the program memory and are used in a similar manner for the data EEPROM ...
Page 80
... PIC18F2331/2431/4331/4431 REGISTER 7-1: EECON1: EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 EEPGD CFGS — bit Settable bit (cannot be cleared in software) Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory ...
Page 81
... BSF INTCON, GIE 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruc- tion ...
Page 82
... PIC18F2331/2431/4331/4431 7.7 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write opera- tions are disabled if either of these mechanisms are enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to “ ...
Page 83
... CFGS IPR2 OSCFIP — PIR2 OSCFIF — PIE2 OSCFIE — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — FREE WRERR WREN — ...
Page 84
... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 84 2010 Microchip Technology Inc. ...
Page 85
... Note 1: The Table Pointer points to a byte in program memory. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces DD through an 8-bit register (TABLAT) ...
Page 86
... PIC18F2331/2431/4331/4431 FIGURE 8-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: The Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in Section 8.5 “Writing to Flash Program 8 ...
Page 87
... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error Note 1: condition. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-x R/W-0 (1) FREE ...
Page 88
... PIC18F2331/2431/4331/4431 8.2.2 TABLAT TABLE LATCH REGISTER – The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch is used to hold 8-bit data during data transfers between program memory and data RAM. 8.2.3 TBLPTR TABLE POINTER – REGISTER The Table Pointer (TBLPTR) addresses a byte within the program memory ...
Page 89
... MOVF TABLAT,W MOVWF WORD_ODD 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. shows the interface between the internal program memory and the TABLAT. ...
Page 90
... PIC18F2331/2431/4331/4431 8.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Larger blocks of program memory can be bulk erased only through the use of an external programmer or ICSP control. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 64 bytes of program memory is erased ...
Page 91
... TBLPTR = xxxxx0 TBLPTR = xxxxx1 Holding Register 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. The EEPROM on-chip timer controls the write time. ...
Page 92
... PIC18F2331/2431/4331/4431 8.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be: 1. Read 64 bytes into RAM. 2. Update data values in RAM as necessary. 3. Load Table Pointer with address being erased the row erase procedure (see “Flash Program Memory Erase 5 ...
Page 93
... POSTINC0,F MOVWF TABLAT TBLWT+* DECFSZ COUNTER GOTO WRITE_WORD_TO_HREGS 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ; number of bytes in erase block ; point to buffer ; Load TBLPTR with the base ; address of the memory block ; 6 LSB = 0 ; read into TABLAT, and inc ; get data ; store data and increment FSR0 ...
Page 94
... PIC18F2331/2431/4331/4431 EXAMPLE 8-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BCF INTCON, GIE MOVLW 55h MOVWF EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR NOP BSF INTCON, GIE DECFSZ COUNTER_HI GOTO PROGRAM_LOOP BCF EECON1, WREN 8.5.2 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value ...
Page 95
... Without Hardware Multiply Unsigned Hardware Multiply Without Hardware Multiply Signed Hardware Multiply 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 9.2 Operation Example 9-1 shows the sequence unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. ...
Page 96
... PIC18F2331/2431/4331/4431 Example 9-3 shows the sequence unsigned multiply. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES<3:0>. EQUATION 9- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L ARG2H:ARG2L RES<3:0> = (ARG1H ARG2H (ARG1H ARG2L 2 (ARG1L ARG2H 2 (ARG1L ...
Page 97
... Individual interrupts can be disabled through their corresponding enable bits. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are devices have ...
Page 98
... PIC18F2331/2431/4331/4431 FIGURE 10-1: INTERRUPT LOGIC TXIF TXIE TXIP ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts High-Priority Interrupt Generation Low-Priority Interrupt Generation TXIF TXIE TXIP ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts DS39616D-page 98 TMR0IF TMR0IE TMR0IP RBIF RBIE ...
Page 99
... RBIF: RB Port Change Interrupt Flag bit least one of the RB<7:4> pins changed state (must be cleared in software None of the RB<7:4> pins have changed state 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the global enable bit ...
Page 100
... PIC18F2331/2431/4331/4431 REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
Page 101
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding Note: enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-0 U-0 INT2IE INT1IE — ...
Page 102
... PIC18F2331/2431/4331/4431 10.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) Registers (PIR1, PIR2 and PIR3). REGISTER 10-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
Page 103
... No TMR1 register capture occurred Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Not used in this mode. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 U-0 R/W-0 EEIF — LVDIF U = Unimplemented bit, read as ‘0’ ...
Page 104
... PIC18F2331/2431/4331/4431 REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4 PTIF: PWM Time Base Interrupt bit 1 = PWM time base matched the value in the PTPER registers. Interrupt is issued according to the postscaler settings ...
Page 105
... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-0 R/W-0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘ ...
Page 106
... PIC18F2331/2431/4331/4431 REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 U-0 U-0 OSCFIE — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6-5 Unimplemented: Read as ‘0’ ...
Page 107
... IC1IE: IC1 Interrupt Enable bit 1 = IC1 interrupt enabled 0 = IC1 interrupt disabled bit 0 TMR5IE: Timer5 Interrupt Enable bit 1 = Timer5 interrupt enabled 0 = Timer5 interrupt disabled 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-0 R/W-0 PTIE IC3DRIE IC2QEIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 108
... PIC18F2331/2431/4331/4431 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three peripheral interrupt priority registers (IPR1, IPR2 and IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
Page 109
... High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-1 U-0 R/W-1 EEIP — LVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-1 — ...
Page 110
... PIC18F2331/2431/4331/4431 REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4 PTIP: PWM Time Base Interrupt Priority bit 1 = High priority ...
Page 111
... For details of bit operation, see bit 1 POR: Power-on Reset Status bit For details of bit operation, see bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Register 5-1 ...
Page 112
... PIC18F2331/2431/4331/4431 10.6 INTx Pin Interrupts External interrupts on the INT0, INT1 and INT2 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge. If the bit is clear, the trigger is on the falling edge. When a valid edge appears on the INTx pin, the corre- sponding flag bit, INTxIF, is set ...
Page 113
... PORT I/O pins have diode protection to V Note 1: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 11.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
Page 114
... PIC18F2331/2431/4331/4431 TABLE 11-1: PORTA I/O SUMMARY TRIS Pin Function Setting RA0/AN0 RA0 0 1 AN0 1 RA1/AN1 RA1 0 1 AN1 1 RA2/AN2/V -/ RA2 REF 0 CAP1/INDX 1 AN2 REF 1 CAP1 1 INDX 1 RA3/AN3/V +/ RA3 REF 0 CAP2/QEA 1 AN3 REF 1 CAP2 1 QEA 1 RA4/AN4/CAP3/ RA4 0 QEB 1 AN4 1 CAP3 1 QEB 1 RA5/AN5/LVDIN ...
Page 115
... RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator Note 1: configuration; otherwise, they are read as ‘0’. ANS5 through ANS8 are available only on the PIC18F4331/4431 devices. 2: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 5 Bit 4 Bit 3 Bit 2 RA5 ...
Page 116
... PIC18F2331/2431/4331/4431 11.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
Page 117
... Don’t care (TRIS bit does not affect port direction or is overridden for this option). All other pin functions are disabled when ICSP or ICD is enabled. Note 1: Single-Supply Programming must be enabled. 2: RD5 is the alternate pin for PWM4. 3: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 I/O I/O Type O DIG LATB<0> data output; not affected by analog input. I TTL PORTB< ...
Page 118
... PIC18F2331/2431/4331/4431 TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 PORTB RB7 RB6 LATB LATB Data Output Register TRISB PORTB Data Direction Register INTCON GIE/GIEH PEIE/GIEL INTCON2 RBPU INTEDG0 INTCON3 INT2IP INT1IP Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. ...
Page 119
... Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 External interrupts, IN0, INT1 and INT2, are placed on RC3, RC4 and RC5 pins, respectively. SSP alternate interface pins, SDI/SDA, SCK/SCL and SDO are placed on RC4, RC5 and RC7 pins, respectively ...
Page 120
... PIC18F2331/2431/4331/4431 TABLE 11-5: PORTC I/O SUMMARY TRIS Pin Function Setting RC0/T1OSO/ RC0 0 T1CKI 1 T1OSO x T1CKI 1 RC1/T1OSI/ RC1 0 CCP2/FLTA 1 T1OSI x CCP2 0 1 FLTA 1 RC2/CCP1/FLTB RC2 0 1 CCP1 0 1 FLTB 1 RC3/T0CKI/ RC3 0 T5CKI/INT0 1 (1) T0CKI 1 (1) T5CKI 1 INT0 1 RC4/INT1/SDI/ RC4 0 SDA 1 INT1 1 (1) ...
Page 121
... PORTC Data Direction Register INTCON GIE/GIEH PEIE/GIEL INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTCON3 INT2IP INT1IP Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTC. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 I/O I/O Type O DIG LATC<7> data output PORTC<7> data input Asynchronous serial receive data input (EUSART module) ...
Page 122
... PIC18F2331/2431/4331/4431 11.4 PORTD, TRISD and LATD Registers PORTD is only available on PIC18F4331/ Note: 4431 devices. PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 123
... SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 Bit 5 PORTD RD7 RD6 LATD LATD Data Output Register TRISD PORTD Data Direction Register 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 I/O I/O Type O DIG LATD<0> data output PORTD<0> data input Timer0 alternate clock input. ...
Page 124
... MOVWF TRISE ; Set RE<0> as input ; RE<1> as output ; RE<2> as input 11.5.1 PORTE IN 28-PIN DEVICES For PIC18F2331/2431 devices, PORTE is not available only available for PIC18F4331/4431 devices. U-0 U-0 R/W-1 — — TRISE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 125
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. Implemented only when Master Clear functionality is disabled (CONFIG3H<7> available for Note 1: PIC18F4331/4431 devices only. ANS5 through ANS8 are available only on PIC18F4331/4431 devices. 2: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 I/O I/O Type O DIG LATE<0> data output; not affected by analog input. ...
Page 126
... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 126 2010 Microchip Technology Inc. ...
Page 127
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Figure 12-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register writable register that controls all the aspects of Timer0, including the prescale selection ...
Page 128
... PIC18F2331/2431/4331/4431 FIGURE 12-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE OSC 0 1 T0CKI pin T0SE T0CS T0PS<2:0> PSA Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. Note: FIGURE 12-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE OSC 0 1 Programmable T0CKI pin ...
Page 129
... TRISA6 Legend: Shaded cells are not used by Timer0. RA6 and RA7 are enabled as I/O pins depending on the oscillator mode selected in Configuration Word 1H. Note 1: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 12.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con- trol (i.e., it can be changed “on-the-fly” during program execution) ...
Page 130
... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 130 2010 Microchip Technology Inc. ...
Page 131
... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Register 13-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON< ...
Page 132
... PIC18F2331/2431/4331/4431 13.1 Timer1 Operation Timer1 can operate in one of these modes: • timer • synchronous counter • asynchronous counter The operating mode is determined by the Timer1 Clock Select bit, TMR1CS (T1CON<1>). FIGURE 13-1: TIMER1 BLOCK DIAGRAM Timer1 Oscillator T1OSO/T1CKI T1OSI (1) T1OSCEN T1CKPS<1:0> T1SYNC TMR1ON Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain ...
Page 133
... Microchip Technology Inc. PIC18F2331/2431/4331/4431 13.3 Timer1 Oscillator Layout Considerations The Timer1 oscillator for PIC18F2331/2431/4331/4431 devices incorporates an additional low-power feature. When this option is selected, it allows the oscillator to automatically reduce its power consumption when the microcontroller is in Sleep mode. During normal device operation, the oscillator draws full current ...
Page 134
... PIC18F2331/2431/4331/4431 13.4 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow, which is latched in Timer1 Interrupt Flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing Timer1 Interrupt Enable bit, TMR1IE (PIE1< ...
Page 135
... T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
Page 136
... PIC18F2331/2431/4331/4431 14.0 TIMER2 MODULE The Timer2 module has the following features: • 8-bit Timer register (TMR2) • 8-bit Period register (PR2) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2 • ...
Page 137
... PR2 Timer2 Period Register Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 14.3 Output of TMR2 The unscaled output of TMR2 is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode ...
Page 138
... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 138 2010 Microchip Technology Inc. ...
Page 139
... Internal clock (T CY bit 0 TMR5ON: Timer5 On bit 1 = Timer5 is enabled 0 = Timer5 is disabled These bits are not implemented on PIC18F2331/2431 devices and read as ‘0’. Note 1: For Timer5 to operate during Sleep mode, T5SYNC must be set. 2: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Timer5 is a general purpose timer/counter that incor- ...
Page 140
... PIC18F2331/2431/4331/4431 FIGURE 15-1: TIMER5 BLOCK DIAGRAM (16-BIT READ/WRITE MODE SHOWN) Noise Filter T5CKI F /4 OSC Internal Clock TMR5CS T5PS<1:0> T5SYNC TMR5ON Special Event Trigger Input 1 from IC1 Timer5 Reset 0 (external) Set TMR5IF Special Event Trigger Output 15.1 Timer5 Operation Timer5 combines two 8-bit registers to function as a 16-bit timer. The TMR5L register is the actual low byte of the timer ...
Page 141
... Reset is present on the Timer5 Reset input. (See Section 15.7 “Timer5 Special Event Trigger for additional information.) Reset Input” 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 15.2 16-Bit Read/Write and Write Modes As noted, the actual high byte of the Timer5 register pair is mapped to TMR5H, which serves as a buffer. ...
Page 142
... PIC18F2331/2431/4331/4431 15.4 Noise Filter The Timer5 module includes an optional input noise filter, designed to reduce spurious signals in noisy operating environments. The filter ensures that the input is not permitted to change until a stable value has been registered for three consecutive sampling clock cycles. The noise filter is part of the input filter network associ- ated with the Motion Feedback Module (see Module” ...
Page 143
... Timer5 Period Register Low Byte T5CON T5SEN RESEN CAP1CON — CAP1REN DFLTCON — FLT4EN Legend: — = unimplemented. Shaded cells are not used by the Timer5 module. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — PTIP IC3DRIP IC2QEIP — ...
Page 144
... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 144 2010 Microchip Technology Inc. ...
Page 145
... Compare mode; initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set) 1010 = Compare mode; generate software interrupt on compare match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode; Special Event Trigger (CCPxIF bit is set) 11xx = PWM mode 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 16-1: CCP Mode Capture Compare PWM 16 ...
Page 146
... PIC18F2331/2431/4331/4431 16.3 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following: • every falling edge • every rising edge • every 4th rising edge • every 16th rising edge The event is selected by control bits, CCP1M< ...
Page 147
... Output Enable Q RC1/CCP2 Pin TRISC<1> Output Enable 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.4.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchro- nized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. ...
Page 148
... PIC18F2331/2431/4331/4431 TABLE 16-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL TMR0IE PIR1 — ADIF PIE1 — ADIE IPR1 — ADIP TRISC PORTC Data Direction Register TMR1L Timer1 Register Low Byte TMR1H Timer1 Register High Byte ...
Page 149
... PWM OUTPUT Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.5.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation: EQUATION 16-1: PWM Period = [(PR2 • 4 • T PWM frequency is defined as 1/[PWM period] ...
Page 150
... PIC18F2331/2431/4331/4431 The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the CCP1 pin is cleared. The ...
Page 151
... Utilizes Input Capture 1 Logic (IC1) • High and Low Velocity Support 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Many of the features for the IC and QEI submodules are fully programmable, creating a flexible peripheral structure that can accommodate a wide range of in-system uses. An overview of the available features ...
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... PIC18F2331/2431/4331/4431 FIGURE 17-1: MOTION FEEDBACK MODULE BLOCK DIAGRAM Special Event Trigger Reset Timer Reset Filter T5CKI Filter CAP3/QEB Filter CAP2/QEA Filter CAP1/INDX T CY Clock Divider CHGIF DS39616D-page 152 TMR5 Reset Control Timer5 Input Capture Logic TMR5<15:0> IC3 IC2 IC1 Postscaler QEB ...
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... Note 1: CAP1BUF register is reconfigured as VELR register when QEI mode is active. 2: QEI generated velocity pulses, vel_out, are downsampled to produce this velocity capture signal. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Input Channel 1 (IC1) includes a Special Event Trigger that can be configured for use in Velocity Measurement mode ...
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... PIC18F2331/2431/4331/4431 FIGURE 17-3: INPUT CAPTURE BLOCK DIAGRAM FOR IC2 AND IC3 CAP2/3 Pin Prescaler Noise Filter FLTCK<2:0> CAP1M<3:0> Q Clocks Note 1: IC2 and IC3 are denoted and 3. 2: CAP2BUF is enabled as POSCNT when QEI mode is active. 3: CAP3BUF is enabled as MAXCNT when QEI mode is active. ...
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... Capture mode, every falling edge 0000 = Input Capture x (ICx) off Special Event Trigger is only available on CAP1. For CAP2 and CAP3, this configuration is unused. Note 1: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Throughout this section, references to Note: registers, registers and bit names that may be asso- ...
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... PIC18F2331/2431/4331/4431 When in Counter mode, the counter must be configured as the synchronous (T5SYNC = 0). When configured in Asynchronous mode, the IC module will not work properly. Note 1: Input capture prescalers are reset (cleared) when the input capture module is disabled (CAPxM = 0000). 2: When the Input Capture mode is ...
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... Measurement mode active on each falling edge detected. 5: TMR5 Reset pulse is activated on the capture edge. The CAP1REN bit has no bearing in this mode. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Timer5 is always reset on the edge when the measurement is first initiated. For example, when the ...
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... PIC18F2331/2431/4331/4431 17.1.3.1 Pulse-Width Measurement Timing Pulse-width measurement accuracy can only be ensured when the pulse-width high and low present on the CAPx input exceeds one T clock cycle. The CY limitations depend on the mode selected: • When CAPxM<3:0> = 0110 (rising to falling edge delay), the CAPx input high pulse width (T must exceed ...
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... Reset on the CAP1 input. In order for the Special Event Trigger Reset to work as the Reset trigger to Timer5, IC1 must be configured in the Special Event Trigger mode (CAP1M<3:0> = 1110 or 1111). 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.1.6 TIMER5 RESET Every input capture trigger can optionally reset (TMR5) ...
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... PIC18F2331/2431/4331/4431 17.1.8 SPECIAL EVENT TRIGGER (CAP1 ONLY) The Special Event Trigger mode (CAP1M<3:0> = 1110 or 1111) enables the Special Event Trigger signal. The trigger signal can be used as the Special Event Trigger Reset input to TMR5, resetting the timer when the specific event happens on IC1 ...
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... CAP2/QEA Filter CAP1/INDX 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The QEI control logic detects the leading edge on the QEA or QEB phase input pins and generates the count pulse, which is sent to the position counter logic. It also samples the index input signal (INDX) and generates the direction of the rotation signal (up/down) and the velocity event signals ...
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... PIC18F2331/2431/4331/4431 17.2.1 QEI CONFIGURATION The QEI module shares its input pins with the Input Capture (IC) module. The inputs are mutually exclusive; only the IC module or the QEI module (but not both) can be enabled at one time. Also, because the IC and QEI are multiplexed to the same input pins, the programmable noise filters can be dedicated to one module only ...
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... Like QEI x2 mode, the position counter can be reset by an input on the pin (QEIM<2:0> = 101 the period match event (QEIM<2:0> = 010). 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.2.3 QEI OPERATION The Position Counter register pair (POSCNTH: POSCNTL) acts as an integrator, whose value is propor- tional to the position of the sensor rotor that corresponds to the number of active edges detected ...
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... PIC18F2331/2431/4331/4431 17.2.3.3 Reset and Update Events The position counter will continue to increment or dec- rement until one of the following events takes place. The type of event and the direction of rotation when it happens determines if a register Reset or update occurs index pulse is detected on the INDX input (QEIM< ...
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... POSCNT = 0 (when decrementing), which occurs on the next QEA falling edge. 3: IC2QEIF is generated on the Q4 rising edge. 4: Position counter is loaded with ‘0’ (which is a rollover event in this case) on POSCNT = MAXCNT. 5: Position counter is loaded with MAXCNT value (1527h) on underflow. 6: IC2QEIF must be cleared in software. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ( QEI /16 ...
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... PIC18F2331/2431/4331/4431 FIGURE 17-11: QEI MODULE RESET TIMING WITH THE INDEX INPUT Forward Note 2 QEA QEB Count (+/-) + (1) POSCNT MAXCNT MAXCNT = 1527 INDX IC2QEIF UP/DOWN Q4 Q1 Position Counter Load Note 1: POSCNT register is shown in QEI x4 Update mode (POSCNT increments on every rising and every falling edge of QEA and QEB input signals). 2: When an INDX Reset pulse is detected, POSCNT is reset to ‘ ...
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... QEB QEA CAP2/QEA INDX CAP1/INDX 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.2.6.1 Velocity Event Timing The event pulses are reduced by a fixed ratio by the velocity pulse divider. The divider is useful for high-speed measurements where the velocity events happen frequently. By producing a single output pulse for a given number of input event pulses, the counter can track larger pulse counts (i ...
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... PIC18F2331/2431/4331/4431 FIGURE 17-13: VELOCITY MEASUREMENT TIMING QEA QEB vel_out velcap (2) TMR5 (2) VELR Old Value (3) cnt_reset (4) IC1IF CAP1REN Instr. Execution BCF PIE2, IC1IE BCF T5CON, VELM Note 1: Timing shown is for QEIM<2:0> = 101, 110 or 111 (x4 Update mode enabled) and the velocity postscaler divide ratio is set to divide-by-4 (PDEC< ...
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... The noise filter output enables are functional in both QEI and IC Operating modes. Note 1: The noise filter is intended for random high-frequency filtering and not continuous high-frequency filtering. Note: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 programmed by the FLTCK<2:0> Configuration bits used as the clock reference to the clock divider CY block ...
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... PIC18F2331/2431/4331/4431 FIGURE 17-14: NOISE FILTER TIMING DIAGRAM (CLOCK DIVIDER = 1: (1) CAP1/INDX Pin (input to filter) (2) CAP1/INDX Input (output from filter Note 1: Only the CAP1/INDX pin input is shown for simplicity. Similar event timing occurs on the CAP2/QEA and CAP3/QEB pins. 2: Noise filtering occurs in the shaded portions of the CAP1 input. ...
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... Legend: — = unimplemented. Shaded cells are not used by the Motion Feedback Module. Register name and function determined by which submodule is selected (IC/QEI, respectively). See Note 1: Section 17.1.10 “Other Operating Modes” 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 172 2010 Microchip Technology Inc. ...
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... PWM outputs disable feature sets PWM outputs to their inactive state when in Debug mode. The Power Control PWM module supports three PWM generators and PIC18F2331/2431 devices, and four generators and eight channels on PIC18F4331/4431 devices. A simpli- fied block diagram of the module is shown in Figure 18-1. ...
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... SEVTCMP Note 1: Only PWM Generator 3 is shown in detail. The other generators are identical; their details are omitted for clarity. 2: PWM Generator 3 and its logic, PWM Channels 6 and 7, and FLTB and its associated logic are not implemented on PIC18F2331/2431 devices. DS39616D-page 174 (1) PWM Generator #3 ...
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... In Complementary modes, the even PWM pins must always be the complement of the corresponding odd PWM pin. For example, PWM0 will be the complement of PWM1, PWM2 will be the complement of PWM3 and so on. The dead-time 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 V DD Dead-Band Generator V ...
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... PIC18F2331/2431/4331/4431 18.1 Control Registers The operation of the PWM module is controlled by a total of 22 registers. Eight of these are used to configure the features of the module: • PWM Timer Control Register 0 (PTCON0) • PWM Timer Control Register 1 (PTCON1) • PWM Control Register 0 (PWMCON0) • PWM Control Register 1 (PWMCON1) • ...
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... The PWM time base can be configured for four different modes of operation: • Free-Running mode • Single-Shot mode • Continuous Up/Down Count mode • Continuous Up/Down Count mode with interrupts for double updates 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PTMR Clock Timer Reset Up/Down Zero Match Timer Direction PTDIR ...
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... PIC18F2331/2431/4331/4431 REGISTER 18-1: PTCON0: PWM TIMER CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 PTOPS3 PTOPS2 PTOPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-4 PTOPS<3:0>: PWM Time Base Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale ...
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... When PWMEN<2:0> = 101, PWM<5:0> outputs are enabled for PIC18F2331/2431 devices; PWM<7:0> 2: outputs are enabled for PIC18F4331/4431 devices. When PWMEN<2:0> = 111, PWM Outputs 1, 3 and 5 are enabled in PIC18F2331/2431 devices; PWM Outputs and 7 are enabled in PIC18F4331/4431 devices. Unimplemented in PIC18F2331/2431 devices; maintain these bits clear. ...
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... PIC18F2331/2431/4331/4431 REGISTER 18-4: PWMCON1: PWM CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 SEVOPS3 SEVOPS2 SEVOPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-4 SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale ...
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... PTMR FFEh PTMR_INT_REQ PTIF bit Note 1: PWM Time Base Period register, PTPER, is loaded with the value, FFFh, for this example. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 18.3.5 PWM TIME BASE POSTSCALER The match output of PTMR can optionally MHz postscaled through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate an interrupt ...
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... PIC18F2331/2431/4331/4431 18.4.2 INTERRUPTS IN SINGLE-SHOT MODE When the PWM time base is in the Single-Shot mode (PTMOD<1:0> = 01), an interrupt event is generated when a match with the PTPER register occurs. The PWM Time Base register (PTMR) is reset to zero on the following input clock edge and the PTEN bit is cleared ...
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... PWM TIME BASE INTERRUPT, CONTINUOUS UP/DOWN COUNT MODE A: PRESCALER = 1 OSC PTMR 002h PTDIR bit PTMR_INT_REQ 1 1 PTIF bit B: PRESCALER = 1 002h PTMR PTDIR bit 1 1 PTMR_INT_REQ PTIF bit Note 1: Interrupt flag bit, PTIF, is sampled here (every Q1). 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 001h 000h 001h 000h ...
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... PIC18F2331/2431/4331/4431 18.4.4 INTERRUPTS IN DOUBLE UPDATE MODE This mode is available in Continuous Up/Down Count mode. In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR register is equal to zero and each time the PTMR matches with PTPER register. Figure 18-8 interrupts in Continuous Up/Down Count mode with double updates ...
Page 185
... EQUATION 18-3: PWM FREQUENCY 1 PWM Frequency = PWM Period 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined from the following formula: EQUATION 18-4: Resolution = The PWM resolutions and frequencies are shown for a ...
Page 186
... PIC18F2331/2431/4331/4431 FIGURE 18-9: PWM PERIOD BUFFER UPDATES IN FREE-RUNNING MODE New PTPER Value = 007 Old PTPER Value = 004 1 0 FIGURE 18-10: PWM PERIOD BUFFER UPDATES IN CONTINUOUS UP/DOWN COUNT MODE New PTPER Value = 007 Old PTPER Value = 004 1 0 DS39616D-page 186 Period Value Loaded from PTPER Register ...
Page 187
... duty cycle match occurs on Q4 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The value in each Duty Cycle register determines the amount of time that the PWM output is in the active state. The upper 12 bits of PDCx holds the actual duty cycle value from PTMRH/L< ...
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... PIC18F2331/2431/4331/4431 18.6.2 DUTY CYCLE REGISTER BUFFERS The four PWM Duty Cycle double-buffered to allow glitchless updates of the PWM outputs. For each duty cycle block, there is a Duty Cycle Buffer register that is accessible by the user and a second Duty Cycle register that holds the actual compare value used in the present PWM period ...
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... First PWM Period 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 New Values Written to Duty Cycle Buffer inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is equal to or greater than the value in the PTPER register ...
Page 190
... PIC18F2331/2431/4331/4431 18.6.5 COMPLEMENTARY PWM OPERATION The Complementary mode of PWM operation is useful to drive one or more power switches in half-bridge configuration as shown in Figure 18-16. This inverter topology is typical for a 3-phase induction motor, brushless DC motor or a 3-phase Uninterruptible Power Supply (UPS) control applications. Each upper/lower power switch pair is fed by a complementary PWM signal ...
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... DEAD-TIME INSERTION FOR COMPLEMENTARY PWM PDC1 Compare Output PWM1 PWM0 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 18.7.1 DEAD-TIME INSERTION Each complementary output pair for the PWM module has a 6-bit down counter used to produce the dead-time insertion. As shown in dead-time unit has a rising and falling edge detector connected to the duty cycle comparison output ...
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... PIC18F2331/2431/4331/4431 REGISTER 18-5: DTCON: DEAD-TIME CONTROL REGISTER R/W-0 R/W-0 R/W-0 DTPS1 DTPS0 DT5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 DTPS<1:0>: Dead-Time Unit A Prescale Select bits 11 = Clock source for dead-time unit Clock source for dead-time unit is F ...
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... F /16 OSC 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 18.7.4 DEAD-TIME DISTORTION Note 1: For small PWM duty cycles, the ratio of dead time to the active PWM time may become large. In this case, the inserted dead time will introduce distortion into waveforms produced by the PWM module ...
Page 194
... PIC18F2331/2431/4331/4431 18.8.2 PWM CHANNEL OVERRIDE PWM output may be manually overridden for each PWM channel by using the appropriate bits in the OVDCOND and OVDCONS registers. The user may select the following signal output options for each PWM output pin operating in the Independent PWM mode: • ...
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... Odd override bit is activated, which causes the even PWM to deactivate. 3. Dead-time insertion. 4. Odd PWM activated after the dead time. 5. Odd override bit is deactivated, which causes the odd PWM to deactivate. 6. Dead-time insertion. 7. Even PWM is activated after the dead time. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 DS39616D-page 195 ...
Page 196
... Output on PWM I/O pin is active when the corresponding PWM output override bit is cleared 0 = Output on PWM I/O pin is inactive when the corresponding PWM output override bit is cleared Unimplemented in PIC18F2331/2431 devices; maintain these bits clear. Note 1: With PWMs configured in Complementary mode, the output of even numbered PWM (PM0,2,4) will be 2: complementary of the output of odd PWM (PWM1,3,5), irrespective of the POUT bit setting ...
Page 197
... TABLE 18-5: PWM OUTPUT OVERRIDE EXAMPLE #2 State OVDCOND (POVD) OVDCONS (POUT) 1 11000011b 00000000b 2 11110000b 00000000b 3 00111100b 00000000b 4 00001111b 00000000b 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 18-22 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 PWM OUTPUT OVERRIDE EXAMPLE # DS39616D-page 197 ...
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... PIC18F2331/2431/4331/4431 18.11 PWM Output and Polarity Control There are three device Configuration bits associated with the PWM module that provide PWM output pin control defined in the CONFIG3L Configuration register. They are: • HPOL • LPOL • PWMPIN These three Configuration bits work in conjunction with the three PWM Enable bits (PWMEN< ...
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... The PWM Fault inputs are FLTA and FLTB, which can come from I/O pins, the CPU or another module. The FLTA and FLTB pins are active-low inputs easy to “OR” many sources to the same input. FLTB and its asso- ciated logic are not implemented on PIC18F2331/2431 devices. The FLTCONFIG register (Register 18-8) defines the settings of FLTA and FLTB inputs ...
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... PIC18F2331/2431/4331/4431 18.12.3 PWM OUTPUTS WHILE IN FAULT CONDITION While in the Fault state (i.e., one or both FLTA and FLTB inputs are active), the PWM output signals are driven into their inactive states. The selection of which PWM outputs are deactivated (while in the Fault state) ...