ATMEGA328-MU Atmel, ATMEGA328-MU Datasheet - Page 145

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ATMEGA328-MU

Manufacturer Part Number
ATMEGA328-MU
Description
IC MCU AVR 32K FLASH 32QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA328-MU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATMEGA32x
Core
AVR
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
ATMEGA328
Supply Current (max)
0.2 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
17. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
17.1
17.2
8271C–AVR–08/10
Features
Overview
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. A simplified
block diagram of the 8-bit Timer/Counter is shown in
I/O pins, refer to
accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific
I/O Register and bit locations are listed in the
The PRTIM2 bit in
enable Timer/Counter2 module.
Figure 17-1. 8-bit Timer/Counter Block Diagram
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Single Channel Counter
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Frequency Generator
10-bit Clock Prescaler
Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B)
Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock
”Pinout ATmega48A/48PA/88A/88PA/168A/168PA/328/328P” on page
”Minimizing Power Consumption” on page 42
Timer/Counter
TCCRnA
OCRnA
TCNTn
OCRnB
=
=
Direction
Count
Clear
Control Logic
TOP
=
TCCRnB
”Register Description” on page
Value
BOTTOM
Fixed
TOP
clk
=
Tn
0
Figure
17-1. For the actual placement of
OCnA
(Int.Req.)
OCnB
(Int.Req.)
TOVn
(Int.Req.)
Clock Select
Generation
Generation
Waveform
Waveform
( From Prescaler )
Detector
Edge
must be written to zero to
159.
OCnA
OCnB
Tn
2. CPU
145

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