ATMEGA328-MU Atmel, ATMEGA328-MU Datasheet - Page 206

• Manufacturer Part Number: ATMEGA328-MU
• Description: IC MCU AVR 32K FLASH 32QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA328-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATMEGA32x
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA328
• Supply Current (max): 0.2 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.4
8271C–AVR–08/10
SPI Data Modes and Timing
Table 20-1.
Note:
There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which
are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are
shown in
signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn function-
ality is summarized in
all ongoing communication for both the Receiver and Transmitter.
Table 20-2.
Figure 20-1. UCPHAn and UCPOLn data transfer timing diagrams.
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Operating Mode
Synchronous Master
mode
UCPOLn
BAUD
f
UBRRn
OSC
0
0
1
1
1. The baud rate is defined to be the transfer rate in bit per second (bps)
Figure
XCK
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
XCK
Equations for Calculating Baud Rate Register Setting
UCPOLn and UCPHAn Functionality-
20-1. Data bits are shifted out and latched in on opposite edges of the XCKn
UCPHAn
Table
Baud rate (in bits per second, bps)
System Oscillator clock frequency
Contents of the UBRRnH and UBRRnL Registers, (0-4095)
0
1
0
1
Equation for Calculating Baud
UCPOL=0
20-2. Note that changing the setting of any of these bits will corrupt
BAUD
SPI Mode
=
0
1
2
3
Rate
-------------------------------------- -
2 UBRRn
(
(1)
f
OSC
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
+
1
)
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
XCK
XCK
Equation for Calculating UBRRn
UBRRn
Trailing Edge
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
UCPOL=1
Value
=
------------------- - 1
2BAUD
f
OSC
–
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