ATTINY24-20MU Atmel, ATTINY24-20MU Datasheet - Page 156
![IC MCU AVR 2K FLASH 20MHZ 20-QFN](/photos/6/87/68751/313-20-qfn_sml.jpg)
ATTINY24-20MU
Manufacturer Part Number
ATTINY24-20MU
Description
IC MCU AVR 2K FLASH 20MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY24-20MU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
12
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-MLF®, QFN
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY24-20MU
Manufacturer:
AVNET
Quantity:
20 000
- Current page: 156 of 238
- Download datasheet (5Mb)
18.6.3
156
ATtiny24/44/84
Reading Device Signature Imprint Table from Firmware
To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and
repeat the procedure above. If successful, the contents of the destination register are as follows.
Refer to
To read the Fuse Extended Byte (FEB), replace the address in the Z-pointer with 0x0002 and
repeat the previous procedure. If successful, the contents of the destination register are as
follows.
Refer to
Byte.
To read the contents of the device signature imprint table, follow the below procedure:
The RSIG and SPMEN bits will auto-clear after three CPU cycles. When RSIG and SPMEN are
cleared, LPM will work as described in the “AVR Instruction Set” description.
See program example below.
Note:
Bit
Rd
Bit
Rd
Assembly Code Example
1. Load the Z-pointer with the table index.
2. Set RSIG and SPMEN bits in SPMCSR.
3. Issue an LPM instruction within three clock cycles.
4. Wait three clock cycles for SPMEN bits to be cleared.
5. Read table data from the LPM destination register.
DSIT_read:
; Uses Z-pointer as table index
ldi
ldi
; Preload SPMCSR bits into R16, then write to SPMCSR
ldi
out SPMCSR, r16
; Issue LPM. Table data will be returned into r17
lpm r17, Z
ret
See
Table 19-4 on page 160
Table 19-3 on page 160
“Code Examples” on page
ZH, 0
ZL, 1
r16, (1<<RSIG)|(1<<SPMEN)
FHB7
FEB7
7
7
FHB6
FEB6
6
6
for detailed description and mapping of the Fuse High Byte.
FHB5
FEB5
for detailed description and mapping of the Fuse Extended
5
5
6.
FHB4
FEB4
4
4
FHB3
FEB3
3
3
FHB2
FEB2
2
2
FHB1
FEB1
1
1
FHB0
FEB0
0
0
8006K–AVR–10/10
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