ATTINY24-20MU Atmel, ATTINY24-20MU Datasheet - Page 108
![IC MCU AVR 2K FLASH 20MHZ 20-QFN](/photos/6/87/68751/313-20-qfn_sml.jpg)
ATTINY24-20MU
Manufacturer Part Number
ATTINY24-20MU
Description
IC MCU AVR 2K FLASH 20MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY24-20MU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
12
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-MLF®, QFN
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY24-20MU
Manufacturer:
AVNET
Quantity:
20 000
- Current page: 108 of 238
- Download datasheet (5Mb)
12.10.1
12.11 Register Description
12.11.1
108
ATtiny24/44/84
Reusing the Temporary High Byte Register
TCCR1A – Timer/Counter1 Control Register A
Note:
The assembly code example requires that the r17:r16 register pair contains the value to be writ-
ten to TCNT1.
If writing to more than one 16-bit register where the high byte is the same for all registers written,
then the high byte only needs to be written once. However, note that the same rule of atomic
operation described previously also applies in this case.
• Bits 7:6 – COM1A1, COM1A0: Compare Output Mode for Channel A
• Bits 5:4 – COM1B1, COM1B0: Compare Output Mode for Channel B
The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respec-
tively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OC1A or OC1B pin must be set in order to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen-
dent of the WGM13:0 bits setting.
when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM).
Bit
0x2F (0x4F)
Read/Write
Initial Value
C Code Example
void TIM16_WriteTCNT1( unsigned int i )
{
}
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Set TCNT1 to i */
TCNT1 = i;
/* Restore global interrupt flag */
SREG = sreg;
See
“Code Examples” on page
COM1A1
R/W
7
0
COM1A0
R/W
6
0
COM1B1
Table 12-2 on page 109
R/W
5
0
6.
COM1B0
R/W
4
0
R
3
–
0
shows the COM1x1:0 bit functionality
R
2
–
0
WGM11
R/W
1
0
WGM10
R/W
0
0
8006K–AVR–10/10
TCCR1A
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