ATTINY24-20MU Atmel, ATTINY24-20MU Datasheet - Page 11
![IC MCU AVR 2K FLASH 20MHZ 20-QFN](/photos/6/87/68751/313-20-qfn_sml.jpg)
ATTINY24-20MU
Manufacturer Part Number
ATTINY24-20MU
Description
IC MCU AVR 2K FLASH 20MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY24-20MU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
12
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-MLF®, QFN
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY24-20MU
Manufacturer:
AVNET
Quantity:
20 000
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- Download datasheet (5Mb)
4.5
4.5.1
8006K–AVR–10/10
Stack Pointer
SPH and SPL — Stack Pointer Register
Figure 4-3.
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-
tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
X-register
Y-register
Z-register
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Read/Write
Initial Value
Initial Value
The X-, Y-, and Z-registers
RAMEND
RAMEND
SP15
SP7
R/W
R/W
15
7
15
7
R27 (0x1B)
15
7
R29 (0x1D)
15
7
R31 (0x1F)
RAMEND
RAMEND
SP14
SP6
R/W
R/W
14
6
RAMEND
RAMEND
SP13
SP5
R/W
R/W
13
5
XH
YH
ZH
0
RAMEND
RAMEND
SP12
SP4
R/W
R/W
12
4
RAMEND
RAMEND
SP11
SP3
R/W
R/W
11
3
0
0
7
R26 (0x1A)
7
R28 (0x1C)
7
R30 (0x1E)
RAMEND
RAMEND
SP10
SP2
R/W
R/W
10
2
ATtiny24/44/84
RAMEND
RAMEND
SP9
SP1
R/W
R/W
9
1
XL
YL
ZL
0
RAMEND
RAMEND
R/W
R/W
SP8
SP0
8
0
SPH
SPL
11
0
0
0
0
0
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