PIC12F635-I/P Microchip Technology, PIC12F635-I/P Datasheet - Page 69

• Manufacturer Part Number: PIC12F635-I/P
• Description: IC MCU FLASH 1KX14 8DIP
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F635-I/P

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 8-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 5
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS- 232/SPI/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029, DV164101, DM163014
• Minimum Operating Temperature: - 40 C
• Data Rom Size: 128 B
• Height: 3.3 mm
• Length: 9.27 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM163029 - BOARD PICDEM FOR MECHATRONICSAC162057 - MPLAB ICD 2 HEADER 14DIPACICE0201 - MPLABICE 8P 300 MIL ADAPTERAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.4
The comparator outputs are read through the
CMCON0 register. These bits are read-only. The
RA2 and RC4 I/O pins. When enabled, multiplexers in
the output path of the RA2 and RC4 pins will switch
and the output of each pin will be the unsynchronized
output of the comparator. The uncertainty of each of
the comparators is related to the input offset voltage
and the response time given in the specifications.
Figure 7-5 and Figure 7-6 show the output block
The TRIS bits will still function as an output enable/
disable for the RA2 and RC4 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C1INV and C2INV bits (CMCON0<5:4>).
Timer1 gate source can be configured to use the T1G
pin or Comparator 2 output as selected by the T1GSS bit
(CMCON1<1>). This feature can be used to time the
duration or interval of analog events. The output of
Comparator 2 can also be synchronized with Timer1 by
setting the C2SYNC bit (CMCON1<0>). When enabled,
the output of Comparator 2 is latched on the falling edge
of the Timer1 clock source. If a prescaler is used with
Timer1, Comparator 2 is latched after the prescaler. To
prevent a race condition, the Comparator 2 output is
latched on the falling edge of the Timer1 clock source
and Timer1 increments on the rising edge of its clock
source. See Figure 7-6, Comparator C2 Output Block
Diagram and Figure 5-1, Timer1 on the PIC12F635/
PIC16F636/639 Block Diagram for more information.
It is recommended to synchronize Comparator 2 with
Timer1 by setting the C2SYNC bit when Comparator 2
is used as the Timer1 gate source. This ensures Timer1
does not miss an increment if Comparator 2 changes
during an increment.
7.5
The comparator interrupt flags are set whenever there
is a change in the output value of its respective
comparator. Software will need to maintain information
about the status of the output bits, as read from
CMCON0<7:6>, to determine the actual change that
has occurred. The CxIF bits (PIR1<4:3>) are the
Comparator Interrupt Flags. These bits must be reset in
software by clearing them to ‘0’. Since it is also possible
to write a ‘1’ to this register, a simulated interrupt may
be initiated.
© 2005 Microchip Technology Inc.
comparator outputs may also be directly output to the
diagrams for Comparator 1 and 2.
Comparator Outputs
Comparator Interrupts
PIC12F635/PIC16F636/639
Preliminary
The CxIE bits (PIE1<4:3>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupts. In
addition, the GIE bit must also be set. If any of these
bits are cleared, the interrupt is not enabled, though the
CxIF bits will still be set if an interrupt condition occurs.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bits CxIF.
Reading CMCON0 will end the mismatch condition and
allow flag bits CxIF to be cleared.
Note:
Any read or write of CMCON0. This will end the
mismatch condition.
Clear flag bits CxIF.
If a change in the CMCON0 register
(CxOUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CxIF (PIR1<4:3>)
interrupt flags may not get set.
DS41232B-page 67