PIC12F675-I/SN Microchip Technology, PIC12F675-I/SN Datasheet - Page 68

• Manufacturer Part Number: PIC12F675-I/SN
• Description: IC MCU CMOS FLSH-BASE 8BIT 8SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F675-I/SN

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 8-SOIC (3.9mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS- 232/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 53270-913
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12F629/675
9.7
The Power-down mode is entered by executing a
SLEEP
If the Watchdog Timer is enabled:
• WDT will be cleared but keeps running
• PD bit in the STATUS register is cleared
• TO bit is set
• Oscillator driver is turned off
• I/O ports maintain the status they had before
For lowest current consumption in this mode, all I/O
pins should be either at V
circuitry drawing current from the I/O pin and the com-
parators and CV
are high-impedance inputs should be pulled high or low
externally to avoid switching currents caused by float-
ing inputs. The T0CKI input should also be at V
V
from on-chip pull-ups on GPIO should be considered.
The MCLR pin must be at a logic high level (V
9.7.1
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
FIGURE 9-13:
DS41190G-page 68
SS
INSTRUCTION FLOW
(INTCON<1>)
Sleep
high-impedance).
Note:
(INTCON<7>)
Note
INTF flag
GIE bit
Instruction
Fetched
Instruction
Executed
CLKOUT
External Reset input on MCLR pin
Watchdog Timer Wake-up (if WDT was enabled)
Interrupt from GP2/INT pin, GPIO change, or a
peripheral interrupt.
for lowest current consumption. The contribution
INT pin
instruction.
OSC1
1:
2:
3:
4:
Power-Down Mode (Sleep)
was executed (driving high, low, or
PC
(4)
It should be noted that a Reset generated
by a WDT Time-out does not drive MCLR
pin low.
WAKE-UP FROM SLEEP
XT, HS or LP Oscillator mode assumed.
T
Sleep delay in INTOSC mode.
GIE =
CLKOUT is not available in XT, HS, LP or EC Osc modes, but shown here for timing reference.
OST
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC) = Sleep
= 1024T
REF
Inst(PC - 1)
1
assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE =
PC
should be disabled. I/O pins that
WAKE-UP FROM SLEEP THROUGH INTERRUPT
OSC
DD
(drawing not to scale). Approximately 1 s delay will be there for RC Osc mode. See Section 12 for wake-up from
, or V
Inst(PC + 1)
Sleep
PC + 1
SS
, with no external
Processor in
Sleep
IHMC
DD
PC + 2
).
or
T
OST
(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Interrupt Latency
Inst(PC + 2)
Inst(PC + 1)
The first event will cause a device Reset. The two latter
events are considered a continuation of program exe-
cution. The TO and PD bits in the STATUS register can
be used to determine the cause of device Reset. The
PD bit, which is set on power-up, is cleared when Sleep
is invoked. TO bit is cleared if WDT Wake-up occurred.
When the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the correspond-
ing interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the
set (enabled), the device executes the instruction after
the
address (0004h). In cases where the execution of the
instruction following
should have an
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
(Note 2)
PC + 2
Note:
SLEEP
SLEEP
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from Sleep. The
SLEEP instruction is completely executed.
Dummy cycle
instruction, then branches to the interrupt
PC + 2
NOP
instruction is being executed, the
SLEEP
SLEEP
after the
 2010 Microchip Technology Inc.
0
Inst(0004h)
Dummy cycle
, execution will continue in-line.
instruction. If the GIE bit is
0004h
is not desirable, the user
SLEEP
instruction.
Inst(0005h)
Inst(0004h)
0005h