PIC12F675-I/SN Microchip Technology, PIC12F675-I/SN Datasheet - Page 25

• Manufacturer Part Number: PIC12F675-I/SN
• Description: IC MCU CMOS FLSH-BASE 8BIT 8SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F675-I/SN

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 8-SOIC (3.9mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS- 232/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 53270-913
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.3.3
Figure 3-2 shows the diagram for this pin. The GP2 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D (PIC12F675 only)
• the clock input for TMR0
• an external edge triggered interrupt
• a digital output from the comparator
FIGURE 3-2:
 2010 Microchip Technology Inc.
TRISIO
Data Bus
PORT
PORT
Interrupt-on-Change
WPU
WPU
TRISIO
IOC
IOC
WR
WR
WR
WR
RD
RD
RD
RD
D
D
D
D
To TMR0
To INT
To A/D Converter
CK
CK
CK
CK
GP2/AN2/T0CKI/INT/COUT
Q
Q
Q
Q
Q
Q
Q
Q
Input Mode
BLOCK DIAGRAM OF GP2
Analog
Enable
COUT
COUT
GPPU
Input Mode
Analog
RD PORT
1
0
Q
Q
Analog
Mode
Input
EN
EN
D
D
V
DD
Weak
V
V
DD
SS
I/O pin
3.3.4
Figure 3-3 shows the diagram for this pin. The GP3 pin
is configurable to function as one of the following:
• a general purpose input
• as Master Clear Reset
FIGURE 3-3:
Data Bus
PORT
Interrupt-on-Change
IOC
TRISIO
IOC
WR
RD
RD
RD
D
CK
GP3/MCLR/V
PIC12F629/675
Q
Q
Reset
BLOCK DIAGRAM OF GP3
V
SS
PP
RD PORT
MCLRE
Q
Q
MCLRE
EN
EN
DS41190G-page 25
D
D
V
SS
I/O pin