PIC12F675-I/SN Microchip Technology, PIC12F675-I/SN Datasheet - Page 26

• Manufacturer Part Number: PIC12F675-I/SN
• Description: IC MCU CMOS FLSH-BASE 8BIT 8SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F675-I/SN

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 8-SOIC (3.9mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS- 232/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 53270-913
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12F629/675
3.3.5
Figure 3-4 shows the diagram for this pin. The GP4 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D (PIC12F675 only)
• a TMR1 gate input
• a crystal/resonator connection
• a clock output
FIGURE 3-4:
DS41190G-page 26
TRISIO
TRISIO
Data Bus
PORT
PORT
Interrupt-on-Change
WPU
WPU
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
WR
WR
WR
WR
IOC
IOC
RD
RD
RD
RD
2: With CLKOUT option.
Enable.
D
D
D
D
To TMR1 T1G
To A/D Converter
CK
CK
CK
CK
GP4/AN3/T1G/OSC2/CLKOUT
Q
Q
Q
Q
Q
Q
Q
Q
Input Mode
BLOCK DIAGRAM OF GP4
Analog
F
OSC1
OSC
INTOSC/
RC/EC
CLKOUT
CLKOUT
Enable
Enable
Input Mode
/4
GPPU
CLKOUT
Analog
Enable
RD PORT
Oscillator
(2)
Modes
Q
Q
1
0
CLK
Circuit
EN
EN
(1)
D
D
V
DD
Weak
V
V
DD
SS
I/O pin
3.3.6
Figure 3-5 shows the diagram for this pin. The GP5 pin
is configurable to function as one of the following:
• a general purpose I/O
• a TMR1 clock input
• a crystal/resonator connection
• a clock input
FIGURE 3-5:
TRISIO
Data Bus
PORT
PORT
WPU
WPU
TRISIO
Interrupt-on-Change
IOC
IOC
WR
WR
WR
WR
RD
RD
RD
RD
Note
D
D
D
D
1: Timer1 LP Oscillator enabled
2: When using Timer1 with LP oscillator, the Schmitt
To TMR1 or CLKGEN
CK
CK
CK
CK
GP5/T1CKI/OSC1/CLKIN
Trigger is by-passed.
Q
Q
Q
Q
Q
Q
Q
Q
BLOCK DIAGRAM OF GP5
INTOSC
 2010 Microchip Technology Inc.
Mode
OSC2
INTOSC
GPPU
Mode
TMR1LPEN
RD PORT
Oscillator
Q
Q
Circuit
EN
EN
D
D
(1)
V
DD
Weak
V
V
DD
SS
I/O pin
(2)