CDB5571 Cirrus Logic Inc, CDB5571 Datasheet - Page 9

• Manufacturer Part Number: CDB5571
• Description: DEV BOARD FOR CS5571 W/MUX
• Manufacturer: Cirrus Logic Inc
• Type: A/Dr

Specifications of CDB5571

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Inputs Per Adc: 2 Single
• Input Range: 2.4 ~ 4.2 V
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5571
• Product: Data Conversion Development Tools
• Conversion Rate: 100 KSPS
• Resolution: 16 bit
• Maximum Clock Frequency: 16 MHz
• Interface Type: SPI
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): - 2.5 V
• For Use With/related Products: CS5571
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1275; CDB5571-1

SWITCHING CHARACTERISTICS
T
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.
DS768PP1
SCLK(i)
Serial Port Timing in SEC Mode (SMODE = VLR)
SCLK(in) Pulse Width (High)
SCLK(in) Pulse Width (Low)
CS hold time (high) after RDY falling
CS hold time (high) after SCLK rising
CS low to SDO out of Hi-Z
Data hold time after SCLK rising
Data setup time before SCLK rising
CS hold time (low) after SCLK rising
RDY rising after SCLK falling
A
MCLK
= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
SDO
RDY
CS
16. SDO will be high impedance when CS is high. In some systems SDO may require a pull-down resistor.
Figure 3. SEC Mode - Continuous SCLK Read Timing (Not to Scale)
Parameter
t
17
t
t
MSB
16
15
t
18
t
19
(CONTINUED)
3/25/08
10:56
(Note 16)
Symbol
t
t
t
t
t
t
t
15
16
17
18
19
20
21
-
-
Min
30
30
10
10
10
10
-
-
-
LSB
t
20
Typ
10
10
10
-
-
-
-
-
-
t
21
SCLK
Max
1
-
-
-
-
-
-
-
-
CS5571
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
9