MT8VDDT6464HDG-335F2 Micron Technology Inc, MT8VDDT6464HDG-335F2 Datasheet - Page 9

• Manufacturer Part Number: MT8VDDT6464HDG-335F2
• Description: MODULE DDR 512MB 200-SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT6464HDG-335F2

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 64b
• Organization: 64Mx64
• Total Density: 512MByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 800mA
• Number Of Elements: 8
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 6:
NOTE:
Table 7:
pdf: 09005aef80b575ca, source: 09005aef806e1d28
DDA8C32_64x64HDG.fm - Rev. D 9/04 EN
1. For a burst length of two, A1
2. For a burst length of four, A2
3. For a burst length of eight, A3
4. Whenever a boundary of the block is reached within a
5. i = 8 (256MB)
LENGTH
BURST
element block; A0 selects the first access within the
block.
element block; A0
block.
element block; A0
block.
given sequence above, the following access wraps
within the block.
i = 9 (512MB, 1GB).
SPEED
-40B
2
4
8
A2 A1 A0
0
0
0
0
1
1
1
1
STARTING
ADDRESS
COLUMN
75 ≤ f ≤ 133
Burst Definition Table
CAS Latency (CL) Table
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
CL = 2
–
–
A0
CLOCK FREQUENCY (MHZ)
A1 select the first access within the
A2 select the first access within the
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ALLOWABLE OPERATING
ORDER OF ACCESSES WITHIN
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
SEQUENTIAL
75 ≤ f ≤ 167
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
CL = 2.5
–
–
0-1
1-0
Ai select the two-data-
Ai select the four-data-
–
Ai select the eight-data-
A BURST
INTERLEAVED
133 ≤ f ≤ 200
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
CL = 3
0-1
1-0
9
reserved for future use and/or test modes. Test modes
and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.
Extended Mode Register
beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 6, Extended Mode Register
Definition Diagram. The extended mode register is
programmed via the LOAD MODE REGISTER com-
mand to the mode register (with BA0 = 1 and BA1 = 0)
and will retain the stored information until it is pro-
grammed again or the device loses power.
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL.
256MB, 512MB (x64, DR) PC3200
COMMAND
COMMAND
COMMAND
All other combinations of values for A7–A12 are
The extended mode register controls functions
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 5: CAS Latency Diagram
CK
CK
CK
Burst Length = 4 in the cases shown
Shown with nominal t AC, t DQSCK, and t DQSQ
READ
READ
READ
T0
T0
T0
200-PIN DDR SODIMM
TRANSITIONING DATA
CL = 2
CL = 2.5
NOP
NOP
NOP
T1
T1
T1
CL = 3
T2
NOP
NOP
NOP
T2
T2
©2004 Micron Technology, Inc.
T2n
T2n
T2n
DON’T CARE
T3
NOP
NOP
NOP
T3
T3
T3n
T3n
T3n
The