MT8VDDT6464HDG-335F2 Micron Technology Inc, MT8VDDT6464HDG-335F2 Datasheet - Page 13

• Manufacturer Part Number: MT8VDDT6464HDG-335F2
• Description: MODULE DDR 512MB 200-SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT6464HDG-335F2

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 64b
• Organization: 64Mx64
• Total Density: 512MByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 800mA
• Number Of Elements: 8
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 12: I
DDR SDRAM component values only
Notes: 1–5, 8, 10, 12, 48; notes appear on pages 17–20; 0°C ≤ T
pdf: 09005aef80b575ca, source: 09005aef806e1d28
DDA8C32_64x64HDG.fm - Rev. D 9/04 EN
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge;
t
and control inputs changing once every two clock cycles
OPERATING CURRENT: One device bank; Active -Read Precharge; Burst = 4;
t
changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-
down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock cycle.
V
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-
down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-
Precharge;
changing twice per clock cycle; Address and other control inputs changing once
per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
I
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank
active; Address and control inputs changing once per clock cycle;
DQ, DM, and DQS inputs changing twice per clock cycle
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE ≤ 0.2V
OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto
precharge,
only during Active READ or WRITE commands
NOTE:
CK =
RC =
OUT
IN
a: Value calculated as one module rank in this operating condition, and all other module ranks in I
b: Value calculated reflects all module ranks in this operating condition.
= V
= 0mA
t
t
CK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address
RC (MIN);
REF
for DQ, DQS, and DM
t
t
RC =
RC =
t
t
CK =
CK =
DD
t
t
t
CK =
RAS (MAX);
RC (MIN);
t
t
CK (MIN); CKE = (LOW)
CK (MIN); CKE = LOW
Specifications and Conditions – 256MB
t
CK (MIN); I
t
CK =
t
CK =
t
OUT
CK (MIN); Address and control inputs change
t
CK (MIN); DQ, DM and DQS inputs
= 0mA; Address and control inputs
t
t
REFC =
REFC = 7.8125µs
t
t
CK =
RC =
t
13
CK =
A
t
RFC (MIN)
t
≤ +70°C; V
CK =
t
256MB, 512MB (x64, DR) PC3200
t
CK (MIN);
RC (MIN);
t
CK (MIN);
t
CK (MIN);
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
, V
DD
Q = +2.6V ±0.1V
I
I
I
I
I
I
I
DD5A
DD4W
I
I
I
SYM
DD3N
I
I
DD2P
DD3P
DD4R
200-PIN DDR SODIMM
DD2F
DD5
DD6
DD7
DD0
DD1
a
a
b
b
a
b
b
b
b
a
a
b
MAX
1,056
2,080
2,056
-40B
556
756
400
320
560
876
32
48
32
DD
UNITS
2p (CKE LOW) mode.
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
©2004 Micron Technology, Inc.
21, 28, 44
21, 28, 44
NOTES
20, 42
20, 42
20, 42
20, 44
24, 44
20, 43
45
20
20
9