MT18HVF6472Y-53EB1 Micron Technology Inc, MT18HVF6472Y-53EB1 Datasheet - Page 4

• Manufacturer Part Number: MT18HVF6472Y-53EB1
• Description: MODULE DDR2 512MB 240-DIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT18HVF6472Y-53EB1

• Memory Type: DDR2 SDRAM
• Memory Size: 512MB
• Speed: 533MT/s
• Package / Case: 240-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5:
PDF: 09005aef82255aba/Source: 09005aef82255a83
HVF18C64_128_256x72G.fm - Rev. B 5/06 EN
DQS0#–DQS17#
DQS0–DQS17,
RAS#, CAS#,
DQ0–DQ63
CK0, CK0#
BA0, BA1
SA0–SA2
CB0–CB7
Symbol
E
A0–A13
RESET#
P
RR
ODT0
V
CKE0
WE#
SDA
AR
V
S0#
SCL
DD
_O
DD
_I
Q
N
UT
Pin Descriptions
Refer to Table 4 on page 3 for more information
(open drain)
(LVCMOS)
(SSTL18)
(SSTL18)
(SSTL18)
(SSTL18)
(SSTL18)
(SSTL18)
(SSTL18)
(SSTL18)
(SSTL18)
(SSTL18)
(SSTL18)
Output
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Source
DRAM,
DRAM
DRAM
DRAM
DRAM
PLL,
SPD
SPD
SPD
PLL
On-die termination: ODT (registered HIGH) enables termination resistance
internal to the DDR2 SDRAM. When enabled, ODT is only applied to the
following pins: DQ, DQS, DQS#, and CB. The ODT input will be ignored if
disabled via the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and negative
edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings
of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW)
deactivates clocking circuitry on the DDR2 SDRAM..
Chip select: S# enables (registered LOW) and disables (registered HIGH) the
command decoder.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command
being entered.
Bank address inputs: BA0–BA1/BA2 define to which device bank an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. BA0–BA1/BA2 define
which mode register, including MR, EMR, EMR(2), and EMR(3), is loaded during
the LOAD MODE command.
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by BA0–BA1/BA2)
or all device banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command.
Parity bit for the address and control bus.
Serial clock for presence-detect: SCL is used to synchronize the presence-
detect data transfer to and from the module.
Presence-detect address inputs: These pins are used to configure the
presence-detect device.
Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power up to ensure that CKE is LOW and DQs are
High-Z.
Data strobe: Output with read data, input with write data for source
synchronous operation. Edge-aligned with read data, center-aligned with
write data. DQS# is only used when differential data strobe mode is enabled
via the LOAD MODE command.
Data input/output: Bidirectional data bus.
Check bits.
Serial presence-detect data: SDA is a bidirectional pin used to transfer
addresses and data into and out of the presence-detect portion of the module.
Parity error found on the address and control bus.
Power supply: 1.8V ±0.1V.
DQ power supply: 1.8V ±0.1V.
1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
Description
©2003 Micron Technology, Inc. All rights reserved.