MT18VDDF12872HY-40BF1 Micron Technology Inc, MT18VDDF12872HY-40BF1 Datasheet - Page 18

• Manufacturer Part Number: MT18VDDF12872HY-40BF1
• Description: MODULE DDR 1GB 200-SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDF12872HY-40BF1

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 400MT/s
• Package / Case: 200-SODIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

pdf: 09005aef80e4880c, source: 09005aef80e487d7
DDAF18C128x72HG.fm - Rev. A 10/04 EN
33. The voltage levels used are derived from a mini-
34. V
35. V
36.
37.
38. During Initialization, V
mum V
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
pulse width
greater than 1/3 of the cycle rate. V
V
pulse width can not be greater than 1/3 of the
cycle rate.
t
t
over
t
referenced to a specific voltage level but specify
when the device output is no longer driving
(
be equal to or less than V
V
even if V
HZ (MAX) will prevail over
RPST (MAX) condition.
RPST end point and
e. The full variation in the ratio of the maximum
f. The full variation in the ratio of the nominal
t
IH
IL
DD
RPST), or begins driving (
TT
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
(MIN) = -1.5V for a pulse width
and V
may be 1.35V maximum during power up,
t
overshoot: V
DQSCK (MIN) +
DD
DD
DD
level and the referenced test load. In
/V
Q must track each other.
DD
3ns and the pulse width can not be
Q are 0.0V, provided a minimum
IH
(MAX) = V
t
RPRE (MAX) condition.
t
RPRE begin point are not
DD
DD
t
Q, V
t
LZ (MIN) will prevail
RPRE).
+ 0.3V. Alternatively,
TT
t
DQSCK (MAX) +
DD
, and V
Q + 1.5V for a
IL
undershoot:
3ns and the
REF
must
18
39. The current Micron part operates below the slow-
40. Random addressing changing and 50 percent of
41. Random addressing changing and 100 percent of
42. CKE must be active (high) during the entire time a
43. IDD2N specifies the DQ, DQS, and DM to be
44. Whenever the operating frequency is altered, not
45. Leakage number reflects the worst case leakage
46. When an input signal is HIGH or LOW, it is
47. This is the DC voltage supplied at the DRAM and
of 42 of series resistance is used between the V
supply and the input pin.
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
data changing at every transfer.
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
driven to a valid high or low logic level. IDD2Q is
similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are similar,
IDD2F is “worst case.”
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
possible through the module pin, not what each
memory device contributes.
defined as a steady state logic HIGH or LOW.
is inclusive of all noise up to 20MHz. Any noise
above 20MHz at the DRAM generated from any
source other than that of the DRAM itself may not
exceed the DC voltage range of +2.6V ±0.1V.
REF later.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1GB (x72, ECC, DR) PC3200
200-PIN DDR SODIMM
©2004 Micron Technology, Inc.
TT