MT18VDDF12872HY-40BF1 Micron Technology Inc, MT18VDDF12872HY-40BF1 Datasheet - Page 17

• Manufacturer Part Number: MT18VDDF12872HY-40BF1
• Description: MODULE DDR 1GB 200-SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDF12872HY-40BF1

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 400MT/s
• Package / Case: 200-SODIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

pdf: 09005aef80e4880c, source: 09005aef80e487d7
DDAF18C128x72HG.fm - Rev. A 10/04 EN
22. The valid data window is derived by achieving
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
25. To maintain a valid level, the transitioning edge of
26. JEDEC specifies CK and CK# input slew rate must
27. DQ and DM input slew rates must not deviate
28. V
29. The clock is allowed up to ±150ps of jitter. Each
160
140
120
100
80
60
40
20
Figure 7: Pull-Down Characteristics
0
0.0
the DRAM controller greater than eight refresh
cycles is not allowed.
other specifications:
(
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55, beyond which functionality is
uncertain.
result in a fail value. CKE is HIGH during
REFRESH command period (
CKE is LOW (i.e., during standby).
the input must:
be 1V/ns (2V/ns differentially).
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
slew rate exceeds 4V/ns, functionality is uncer-
tain. For -40B, slew rates must be 0.5 V/ns.
not active while any bank is active.
timing parameter is allowed to vary by the same
DH for each 100mv/ns reduction in slew rate. If
a. Sustain a constant slew rate from the current
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
t
QH =
DD
AC level through to the target AC level, V
or V
maintain at least the target DC level, V
or V
must not vary more than 4 percent if CKE is
t
IH
IH
HP -
0.5
(AC).
(DC).
t
QHS). The data valid window derates
1.0
t
HP (
V
V
OUT
OUT
(V)
(V)
t
CK/2),
1.5
t
RFC [MIN]) else
t
DQSQ, and
2.0
Minimum
t
DS and
IL
IL
(DC)
(AC)
t
QH
2.5
17
30. READs and WRITEs with auto precharge are not
31. Any positive glitch must be less than 1/3 of the
32. Normal Output Drive Curves:
-100
-120
-140
-160
-180
-200
-20
-40
-60
-80
0
0.0
amount.
and
CK and CK# inputs, collectively during bank
active.
allowed to be issued until
fied prior to the internal precharge command
being issued.
clock and not more than +300mV or 2.9V, which-
ever is less. Any negative glitch must be less than
1/3 of the clock cycle and not exceed either -
200mV or 2.4V, whichever is more positive. The
average cannot be below the +2.6V minimum.
Figure 8: Pull-Up Characteristics
a. The full variation in driver pull-down current
b. The variation in driver pull-down current
c. The full variation in driver pull-up current
d. The variation in driver pull-up current within
Micron Technology, Inc., reserves the right to change products or specifications without notice.
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 7,
Pull-Down Characteristics.
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 7, Pull-Down Characteristics.
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 8,
Pull-Up Characteristics.
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
8, Pull-Up Characteristics.
t
1GB (x72, ECC, DR) PC3200
CH minimum actually applied to the device
t
0.5
HP min is the lesser of
200-PIN DDR SODIMM
1.0
V
DD
Q - V
OUT
t
RAS(MIN) can be satis-
(V)
1.5
©2004 Micron Technology, Inc.
t
CL minimum
2.0
2.5