MAX8720ETX+ Maxim Integrated Products, MAX8720ETX+ Datasheet - Page 20

• Manufacturer Part Number: MAX8720ETX+
• Description: IC CNTRL VID STP DWN 36-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX8720ETX+

• Applications: Controller, CPU GPU
• Voltage - Input: 2 ~ 28 V
• Number Of Outputs: 1
• Voltage - Output: 0.28 ~ 1.85 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-TQFN Exposed Pad
• Output Voltage: 0.275 V to 1.85 V
• Input Voltage: 2 V to 28 V
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When the CPU suspends operation (SUS = high), the
controller overrides the 6-bit VID DAC code set by
D0–D5, and slews the output voltage to the target volt-
age set by the S0, S1 inputs. During the transition, the
MAX8720 blanks both PGOOD thresholds (PGOOD
forced high impedance) until the slew-rate controller
reaches the suspend-mode voltage, plus 8 extra R
clocks. After this blanking time expires, the MAX8720
automatically switches to a pulse-skipping control
scheme regardless of SKIP.
The MAX8720 is designed to perform output-voltage
transitions in a controlled manner, automatically mini-
mizing input surge currents. This feature allows the cir-
cuit designer to achieve nearly ideal transitions,
guaranteeing just-in-time arrival at the new output-volt-
age level with the lowest possible peak currents for a
given output capacitance. This makes the IC ideal for
CPUs and GPUs that operate at different voltages.
At the beginning of an output-voltage transition (VID
change or SUS level change), the MAX8720 enters
forced-PWM mode and blanks the PGOOD output
(forced high impedance). PGOOD remains blanked
during the transition and is re-enabled when the slew-
rate controller has set the internal DAC to the final value
and 8 additional slew-rate clock periods have passed.
The slew-rate clock frequency (set by resistor R
must be set fast enough to ensure that the longest
required transition is completed within the allowed tran-
sition time.
The output-voltage transition is performed in 25mV
steps, preceded by a delay and followed by one addi-
Dynamically Adjustable 6-Bit VID
Step-Down Controller
Table 5. Suspend-Mode DAC Codes
20
GND
GND
GND
GND
REF
REF
REF
REF
S1
______________________________________________________________________________________
OPEN
OPEN
GND
GND
REF
V
REF
V
S0
CC
CC
Output-Voltage-Transition Timing
V
0.650
0.625
0.600
0.575
0.550
0.525
0.500
0.475
OUT
OPEN
OPEN
OPEN
OPEN
V
V
V
V
S1
CC
CC
CC
CC
OPEN
OPEN
GND
GND
REF
V
REF
V
S0
CC
CC
V
0.450
0.425
0.400
0.375
0.350
0.325
0.300
0.275
OUT
TIME
TIME
)
tional clock period. The total time for a transition
depends on R
accuracy of the MAX8720’s slew-rate clock, and is not
dependent on the total output capacitance. The greater
the output capacitance, the higher the surge current
required for the transition. The MAX8720 automatically
controls the current to the minimum level required to
complete the transition in the calculated time, as long
as the surge current is less than the current limit set by
ILIM. The transition time is given by:
where f
original DAC setting, V
t
See Time Frequency Accuracy in the Electrical Char-
acteristics table for f
range of R
1.22µs to 26µs per 25mV step. Although the DAC takes
discrete 25mV steps, the output filter makes the transi-
tions relatively smooth. The average inductor current
required to make an output-voltage transition is:
When the MAX8720 enters suspend mode while config-
ured for forced-PWM operation (SKIP pulled high), the
controller ramps the output voltage down to the S0, S1
programmed voltage at the slew rate determined by
R
impedance) until the transition is completed plus 8 extra
R
selected S0, S1 DAC voltage. After this blanking time
expires, the controller enters pulse-skipping operation.
When exiting suspend mode (SUS pulled low), the
MAX8720 immediately enters forced-PWM mode and
ramps the output up at the slew rate set by R
controller blanks PGOOD (forced high impedance) until
the transition is completed plus 8 extra R
the internal target voltage equals the selected D0–D5
DAC voltage.
DELAY
TIME
TIME
. The controller blanks PGOOD (forced high
clocks—the internal target voltage equals the
SLEW
ranges from zero to a maximum of 2 / f
t
TIME
TRANS
I
L AVE
= 150kHz x 120kΩ / R
(
TIME
is 22kΩ to 470kΩ, corresponding to
)
=
(Forced-PWM Operation Selected)
=
, the voltage difference, and the
|
25
V
C
NEW
OLD
SLEW
OUT
mV f
−
×
is the new DAC setting, and
×
V
SLEW
accuracy. The practical
NEW
25
mV
Suspend Transition
|
+
×
TIME
t
DELAY
f
SLEW
TIME
, V
OLD
TIME
clocks—
SLEW
is the
. The
.