MAX8744ETJ+ Maxim Integrated Products, MAX8744ETJ+ Datasheet - Page 19

• Manufacturer Part Number: MAX8744ETJ+
• Description: IC CNTRLR PWR SUP QUAD 32TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX8744ETJ+

• Applications: Controller, Notebook Computers
• Voltage - Input: 6 ~ 26 V
• Number Of Outputs: 4
• Voltage - Output: 3.3V, 5V, 1 ~ 26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFN Exposed Pad
• Duty Cycle (max): 99 %
• Output Voltage: 3.315 V, 5.015 V, 2 V to 5.5 V
• Mounting Style: SMD/SMT
• Switching Frequency: 200 KHz, 300 KHz, 500 KHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Synchronous Pin: No
• Topology: Boost, Flyback, Forward
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

making the threshold to exit shutdown less accurate. To
guarantee startup, drive SHDN above 2V (SHDN input
rising-edge trip level). For automatic shutdown and
startup, connect SHDN to V
edge threshold on SHDN can be used to detect a spe-
cific input voltage level and shut the device down. Once
in shutdown, the 1.6V rising-edge threshold activates,
providing sufficient hysteresis for most applications.
Power-on reset (POR) occurs when LDO5 rises above
approximately 1V, resetting the undervoltage, overvolt-
age, and thermal-shutdown fault latches. The POR cir-
cuit also ensures that the low-side drivers are pulled
high until the SMPS controllers are activated. Figure 2
is the MAX8744/MAX8745 block diagram.
The LDO5 input undervoltage-lockout (UVLO) circuitry
inhibits switching if the 5V bias supply (LDO5) is below
its 4V UVLO threshold. Once the 5V bias supply
(LDO5) rises above this input UVLO threshold and the
SMPS controllers are enabled (ON_ driven high), the
SMPS controllers start switching, and the output volt-
ages begin to ramp up using soft-start. If the LDO5
voltage drops below the UVLO threshold, the controller
stops switching and pulls the low-side gate drivers low
until the LDO5 voltage recovers or drops below the
POR threshold.
The internal soft-start gradually increases the feedback
voltage with a 1V/ms slew rate. Therefore, the outputs
Table 3. Operating Mode Truth Table
* SHDN is an accurate, low-voltage logic input with 1V falling-edge threshold voltage and 1.6V rising-edge threshold voltage. ON3
and ON5 are tri-level CMOS logic inputs, a logic-low voltage is less than 0.8V, a logic-high voltage is greater than 2.4V, and the mid-
dle-logic level is between 1.7V and 2.3V (see the Electrical Characteristics table).
Shutdown Mode
Standby Mode
Normal Operation
3.3V SMPS Active
5V SMPS Active
Normal Operation
(Delayed 5V SMPS
Startup)
Normal Operation
(Delayed 3.3V SMPS
Startup)
MODE
Supply Controllers for Notebook Computers
High-Efficiency, Quad-Output, Main Power-
SMPS POR, UVLO, and Soft-Start
______________________________________________________________________________________
SHDN
High
High
High
High
High
High
Low
IN
. The accurate 1V falling-
INPUTS*
High
High
High
ON5
Low
Low
Ref
X
High
High
High
ON3
Low
Low
Ref
X
OFF
ON
ON
ON
OFF
LDO5 to CSL5 bypass
switch enabled
OFF
LDO5 to CSL5 bypass
switch enabled
OFF
LDO5 to CSL5 bypass
switch enabled
LDO5
reach their nominal regulation voltage 2ms after the
SMPS controllers are enabled (see the Soft-Start
Waveform in the Typical Operating Characteristics ).
This gradual slew rate effectively reduces the input
surge current by minimizing the current required to
charge the output capacitors (I
V
ON3 and ON5 control SMPS power-up sequencing.
ON3 or ON5 rising above 2.4V enables the respective
outputs. ON3 or ON5 falling below 1.6V disables the
respective outputs. Driving ON_ below 0.8V clears the
overvoltage, undervoltage, and thermal fault latches.
Connecting ON3 or ON5 to REF forces the respective
outputs off while the other output is below regulation
and starts after that output regulates. The second
SMPS remains on until the first SMPS turns off, the
device shuts down, a fault occurs, or LDO5 goes into
UVLO. Both supplies begin their power-down
sequence immediately when the first supply turns off.
When the switching regulators are disabled—when
ON_ or SHDN is pulled low, or when an output under-
voltage fault occurs—the internal soft-shutdown gradu-
ally decreases the feedback voltage with a 0.5V/ms
slew rate. Therefore, the regulation voltage drops to 0V
OUT(NOM)
/t
SMPS Enable Controls (ON3, ON5)
SLEW
ON
OFF
OFF
ON
OFF
ON
ON
Power-up after 3.3V
SMPS is in regulation
).
Output Discharge (Soft-Shutdown)
OUTPUTS
5V SMPS
SMPS Power-Up Sequencing
OUT
OFF
OFF
ON
ON
OFF
ON
ON
Power-up after 5V
SMPS is in regulation
= I
LOAD
3V SMPS
+ C
OUT
19
x