MAX8770GTL+T Maxim Integrated Products, MAX8770GTL+T Datasheet - Page 42

• Manufacturer Part Number: MAX8770GTL+T
• Description: IC CTLR PS 2/1PH QUICK PWM 40QFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX8770GTL+T

• Applications: Controller, Intel IMVP-6
• Voltage - Input: 4 ~ 26 V
• Number Of Outputs: 1
• Voltage - Output: 0.125 ~ 1.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PWM Controller for IMVP-6+ CPU Core Power Supplies
age, source inductance, and PC board layout charac-
teristics. The following switching-loss calculation pro-
vides only a very rough estimate and is no substitute for
breadboard evaluation, preferably including verification
using a thermocouple mounted on N
where C
Q
FET, and I
rent (2.2A typ).
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied due to the squared term in the C x
V
MOSFET chosen for adequate R
voltages becomes extraordinarily hot when biased from
V
lower parasitic capacitance.
For the low-side MOSFET (N
dissipation always occurs at maximum input voltage:
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
I
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, you can “overdesign” the
circuit to tolerate:
where I
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good size heatsink to handle the overload
power dissipation.
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL
42
LOAD(MAX)
IN
IN(MAX)
G(SW)
I
LOAD
⎛
⎜
⎝
2
V
______________________________________________________________________________________
IN MAX LOAD SW
x ƒ
=
(
⎡
⎢
⎢
⎣
VALLEY(MAX)
is the charge needed to turn on the N
η
OSS
SW
1
η
=
, consider choosing another MOSFET with
MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-
TOTAL VALLEY MAX
TOTAL
GATE
−
, but are not quite high enough to exceed
)
η
I
switching-loss equation. If the high-side
⎛
⎜
⎝
TOTAL
is the N
V
PD N
IN MAX
I
V
is the peak gate-drive source/sink cur-
PD N RESISTIVE
OUT
(
f
(
(
⎛
⎜
⎝
I
H
H
VALLEY MAX
)
⎞
⎟
⎠
is the maximum valley current
L
(
⎞
⎟
⎠
MOSFET’s output capacitance,
SWITCHING
⎛
⎜
⎝
⎤
⎥
⎥
⎦
Q
⎛
⎜
⎝
I
GATE
G SW
η
)
I
(
LOAD
(
TOTAL
L
+
), the worst-case power
⎛
⎜
⎝
)
I
⎞
⎟ +
⎠
DS(ON)
)
LOAD MAX
+
)
⎞
⎟
⎠
H
)
2
:
=
∆
=
C
(
R
I
2
INDUCTOR
OSS IN SW
DS ON
at low battery
(
2
)
LIR
V
2
)
2
H
⎞
⎟
⎠
f
MOS-
⎞
⎟
⎠
Choose a Schottky diode (D
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. Select a
diode that can handle the load current per phase dur-
ing the dead times. This diode is optional and can be
removed if efficiency is not critical.
The boost capacitors (C
enough to handle the gate-charging requirements of
the high-side MOSFETs. Typically, 0.1µF ceramic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current appli-
cations driving large, high-side MOSFETs require boost
capacitors larger than 0.1µF. For these applications,
select the boost capacitors to avoid discharging the
capacitor more than 200mV while charging the high
side MOSFETs’ gates:
where N is the number of high side MOSFETs used for
one regulator, and Q
in the MOSFET’s data sheet. For example, assume (2)
IRF7811W n-channel MOSFETs are used on the high
side. According to the manufacturer’s data sheet, a sin-
gle IRF7811W has a maximum gate charge of 24nC
(V
boost capacitance would be:
Selecting the closest standard value, this example
requires a 0.22µF ceramic capacitor.
The current-balance compensation capacitor (C
integrates the difference between the main and sec-
ondary current-sense voltages. The internal compensa-
tion resistor (R
response by increasing the phase margin. This allows
the dynamics of the current-balance loop to be opti-
mized. Excessively large capacitor values increase the
integration time constant, resulting in larger current dif-
ferences between the phases during transients.
Excessively small capacitor values allow the current
loop to respond cycle-by-cycle, but can result in small
DC current variations between the phases. Likewise,
excessively large resistor values can also cause DC
current variations between the phases. Small resistor
values reduce the phase margin, resulting in marginal
GS
= 5V). Using the above equation, the required
Current-Balance Compensation (CCI)
C
BST
C
CCI
BST
=
GATE
®
2
= 200kΩ) improves transient
=
200
IMVP-6 LICENSEES
×
BST
N
24
is the gate charge specified
mV
×
200
) must be selected large
nC
L
) with a forward voltage
Q
mV
Boost Capacitors
GATE
=
0 24µ
.
F
CCI
)