MAX8770GTL+T Maxim Integrated Products, MAX8770GTL+T Datasheet - Page 26

• Manufacturer Part Number: MAX8770GTL+T
• Description: IC CTLR PS 2/1PH QUICK PWM 40QFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX8770GTL+T

• Applications: Controller, Intel IMVP-6
• Voltage - Input: 4 ~ 26 V
• Number Of Outputs: 1
• Voltage - Output: 0.125 ~ 1.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PWM Controller for IMVP-6+ CPU Core Power Supplies
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL
Table 3. Operating Mode Truth Table
*Multiphase operation = All enabled phases active.
26
Falling
SHDN
Rising
High
High
High
High
High
Low
______________________________________________________________________________________
MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-
DPRSTP
High
Low
X
X
X
X
X
X
INPUTS
DPRSLPVR
High
High
Low
Low
X
X
X
X
High
Low
PSI
X
X
X
X
X
X
Multiphase
forced-PWM,
1/8 R
rate
1-phase forced
1/4 R
OPERATION*
1/8 R
1-phase pulse
1-phase pulse
normal R
normal R
normal R
forced PWM;
forced PWM
Multiphase
Multiphase
DISABLED
DISABLED
skipping,
skipping,
slew rate
slew rate
slew rate
PHASE
PWM;
TIME
TIME
TIME
rate
rate
TIME
TIME
TIME
slew
slew
slew
Low-Power Shutdown Mode. DL1 and DL2 forced high,
and the controller is disabled. The supply current drops to
1µA (max).
Startup/Boot. When SHDN is pulled high, the
MAX8770/MAX8771/MAX8772 begin the startup sequence.
Once the REF is above 1.84V, the controller enables the PWM
controller and ramps the output voltage up to the boot
voltage. See Figure 9.
Full Power. The no-load output voltage is determined by the
selected VID DAC code (D0–D6, Table 4).
Intermediate Power. The no-load output voltage is determined
by the selected VID DAC code (D0–D6, Table 4). When PSI is
pulled low, the MAX8770/MAX8771/MAX8772 immediately
disable phase 2—DH2, and DL2 pulled low.
Deeper Sleep Mode. The no-load output voltage is
determined by the selected VID DAC code (D0–D6, Table 4).
When DPRSLPVR is pulled high, the MAX8770/MAX8771/
MAX8772 immediately enter 1-phase pulse-skipping
operation allowing automatic PWM/PFM switchover under
light loads. The PWRGD and CLKEN upper thresholds are
blanked. DH2 and DL2 are pulled low.
Deeper Sleep Slow-Exit Mode. The no-load output voltage is
determined by the selected VID DAC code (D0–D6, Table 4).
When DPRSTP is pulled high while DPRSLPVR is already
high, the MAX8770/MAX8771/MAX8772 remain in 1-phase
pulse-skipping operation, allowing automatic PWM/PFM
switchover under light loads. The PWRGD and CLKEN upper
thresholds are blanked. DH2 and DL2 are pulled low.
Shutdown. When SHDN is pulled low, the
MAX8770/MAX8771/MAX8772 immediately pull PWRGD and
PHASEGD low, CLKEN becomes high impedance, all
enabled phases are activated, and the output voltage is
ramped down to ground. Once the output reaches zero, the
controller enters the low-power shutdown state. See Figure 9.
Fault Mode. The fault latch has been set by the MAX8770/
MAX8771/MAX8772 UVP or thermal shutdown protection, or
by the MAX8771 OVP protection. The controller remains in
FAULT mode until V
CC
OPERATING MODE
power is cycled or SHDN toggled.
®
IMVP-6 LICENSEES