MAX8770GTL+T Maxim Integrated Products, MAX8770GTL+T Datasheet - Page 17

• Manufacturer Part Number: MAX8770GTL+T
• Description: IC CTLR PS 2/1PH QUICK PWM 40QFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX8770GTL+T

• Applications: Controller, Intel IMVP-6
• Voltage - Input: 4 ~ 26 V
• Number Of Outputs: 1
• Voltage - Output: 0.125 ~ 1.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PWM Controller for IMVP-6+ CPU Core Power Supplies
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL
31–37
PIN
EP
38
39
40
MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-
DPRSLPVR
DPRSTP
D0–D6
NAME
SHDN
EP
______________________________________________________________________________________
Low-Voltage VID DAC Code Input. The D0–D6 inputs do not have internal pullups. These 1.0V logic inputs
are designed to interface directly with the CPU. The output voltage is set by the VID code indicated by the
logic-level voltages on D0–D6 (see Table 4).
Shutdown Control Input. This input cannot withstand the battery voltage. Connect to V
operation. Connect to ground to put the IC into its 1µA max shutdown state. During startup, the output
voltage is ramped up to the boot voltage slowly at a slew rate that is 1/8 the slew rate set by the TIME
resistor. During the transition from normal operation to shutdown, the output voltage is ramped down at the
same slow slew rate. Forcing SHDN to 11V~13V disables both OVP and UVP protection circuits, clears the
fault latch, disables transient phase overlap, and disables the BST_ charging switches. Do not connect
SHDN to > 13V.
Logic Input to Indicate Power Usage. PSI and DPRSLPVR together determine the operating mode as
shown in the truth table below. The PWRGD upper threshold is blanked when the part is in skip mode. The
part is forced into full-phase PWM mode during startup, while in boot mode, during the transition
from boot mode to VID mode, and during shutdown.
DPRSLPVR
1.0V Logic-Input Signal. This signal from the system is usually the logical complement of the DPRSLPVR
signal. However, there is a special condition during C4 exit when both DPRSTP and DPRSLPVR could
temporarily be simultaneously high. If this happens, the slew rate reduces to 1/4 of the normal (R
based) slew rate for the duration of this condition. The slew rate returns to normal when this condition is
exited. Note that only DPRSLPVR and PSI (but not DPRSTP) determine the mode of operation (PWM vs.
skip) and the number of active phases:
DPRSLPVR
Exposed Backside Pad. Connect the exposed backside pad to AGND.
1
1
0
0
0
0
1
1
PSI
DPRSTP
0
1
0
1
0
1
0
1
Mode
Very low current (1-phase skip)
Low current (approximately 3A) (1-phase skip)
Intermediate power potential (1-phase PWM)
Max power potential (full-phase PWM: number of phases by CSP2)
Functionality
Normal slew rate, number of phases set by PSI and CSP2
(DPRSLPVR low → → → → DPRSTP is ignored)
Normal slew rate, number of phases set by PSI and CSP2
(DPRSLPVR low → → → → DPRSTP is ignored)
Normal slew rate, 1-phase skip mode
Slew rate reduced to 1/4 of normal,1-phase skip mode
FUNCTION
Pin Description (continued)
®
IMVP-6 LICENSEES
CC
for normal
TIME
-
17