MAX8770GTL+T Maxim Integrated Products, MAX8770GTL+T Datasheet - Page 38

• Manufacturer Part Number: MAX8770GTL+T
• Description: IC CTLR PS 2/1PH QUICK PWM 40QFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX8770GTL+T

• Applications: Controller, Intel IMVP-6
• Voltage - Input: 4 ~ 26 V
• Number Of Outputs: 1
• Voltage - Output: 0.125 ~ 1.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PWM Controller for IMVP-6+ CPU Core Power Supplies
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL
Figure 10. Gate Drive Circuit
MAX8771/MAX8772 interprets the MOSFET gates as
“off” while charge actually remains. Use very short,
wide traces (50 mils to 100 mils wide if the MOSFET is
1in from the driver).
The internal pulldown transistor that drives DL low is
robust, with a 0.25Ω (typ) on-resistance. This helps pre-
vent DL from being pulled up due to capacitive cou-
pling from the drain to the gate of the low-side
MOSFETs when the inductor node (LX) quickly switch-
es from ground to V
ages and long inductive driver traces may require
rising LX edges that do not pull up the low-side
MOSFETs’ gate, causing shoot-through currents. The
capacitive coupling between LX and DL created by the
MOSFET’s gate-to-drain capacitance (C
source capacitance (C
board parasitics should not exceed the following mini-
mum threshold:
Typically, adding a 4700pF between DL and power
ground (C
38
(R
(C
BST
______________________________________________________________________________________
NL
)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE
)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE
SWITCHING NODE RISE TIME.
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS
MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-
NL
in Figure 10), close to the low-side
PGND
BST
V
V
DH
DL
LX
DD
GS TH
IN
(
. Applications with high-input volt-
C
(R
BYP
(C
)
BST
C
ISS
>
NL
BST
)*
)*
V
IN
- C
⎛
⎜
⎝
C
C
RSS
RSS
ISS
), and additional
⎞
⎟
⎠
N
N
H
L
RSS
INPUT (V
L
), gate-to-
IN
)
MOSFETs, greatly reduces coupling. Do not exceed
22nF of total gate capacitance to prevent excessive
turn-off delays.
Alternatively, shoot-through currents may be caused by
a combination of fast high-side MOSFETs and slow low-
side MOSFETs. If the turn-off delay time of the low-side
MOSFET is too long, the high-side MOSFETs can turn
on before the low-side MOSFETs have actually turned
off. Adding a resistor less than 5Ω in series with BST
slows down the high-side MOSFET turn-on time, elimi-
nating the shoot-through currents without degrading
the turn-off time (R
high-side MOSFET also reduces the LX node rise time,
thereby reducing EMI and high-frequency coupling
responsible for switching noise.
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switch-
ing frequency and inductor operating point, and the fol-
lowing four factors dictate the rest of the design:
• Input voltage range: The maximum value (V
• Maximum load current: There are two values to
For multiphase systems, each phase supports a frac-
tion of the load, depending on the current balancing.
When properly balanced, the load current is evenly dis-
tributed among each phase:
where η
must accommodate the worst-case high-AC adapter
voltage. The minimum value (V
for the lowest input voltage after drops due to con-
nectors, fuses, and battery selector switches. If there
is a choice at all, lower input voltages result in better
efficiency.
consider. The peak load current (I
mines the instantaneous component stresses and fil-
tering requirements, and thus drives output capacitor
selection, inductor saturation rating, and the design
of the current-limit circuit. The continuous load cur-
rent (I
thus drives the selection of input capacitors,
MOSFETs, and other critical heat-contributing com-
ponents. Modern notebook CPUs generally exhibit
I
LOAD
TOTAL
LOAD
= I
LOAD(MAX)
) determines the thermal stresses and
is the total number of active phases.
I
LOAD PHASE
Multiphase Quick-PWM
BST
®
(
x 80%.
in Figure 10). Slowing down the
IMVP-6 LICENSEES
Design Procedure
)
=
η
I
LOAD
TOTAL
IN(MIN)
LOAD(MAX)
) must account
IN(MAX)
) deter-
)