MAX8770GTL+T Maxim Integrated Products, MAX8770GTL+T Datasheet - Page 29

• Manufacturer Part Number: MAX8770GTL+T
• Description: IC CTLR PS 2/1PH QUICK PWM 40QFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX8770GTL+T

• Applications: Controller, Intel IMVP-6
• Voltage - Input: 4 ~ 26 V
• Number Of Outputs: 1
• Voltage - Output: 0.125 ~ 1.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PWM Controller for IMVP-6+ CPU Core Power Supplies
When the processor enters low-power deeper sleep
mode, the IMVP-6 CPU sets the VID DAC code to a
lower output voltage and drives DPRSLPVR high. The
MAX8770/MAX8771/MAX8772 respond by slewing the
internal target voltage to the new DAC code, switching
to single-phase operation, and letting the output volt-
age gradually drift down to the deeper sleep voltage.
During the transition, the MAX8770/MAX8771/MAX8772
blank both the upper and lower PWRGD and CLKEN
thresholds until 20µs after the internal target reaches
the deeper sleep voltage. Once the 20µs timer expires,
the MAX8770/MAX8771/MAX8772 reenable the lower
PWRGD and CLKEN threshold, but keep the upper
threshold blanked. PHASEGD remains blanked high
impedance while DPRSLPVR is high.
The MAX8770/MAX8771/MAX8772 perform mode tran-
sitions in a controlled manner, automatically minimizing
input surge currents. This feature allows the circuit
designer to achieve nearly ideal transitions, guarantee-
ing just-in-time arrival at the new output-voltage level
with the lowest possible peak currents for a given out-
put capacitance.
At the beginning of an output-voltage transition, the
MAX8770/MAX8771/MAX8772 blank PHASEGD,
CLKEN, and PWRGD upper and lower thresholds, pre-
venting the open-drain outputs from changing states
during the transition. The controller enables the lower
CLKEN and PWRGD threshold approximately 20µs
after the slew-rate controller reaches the target output
voltage, but the upper CLKEN and PWRGD threshold is
enabled only if the controller remains in forced-PWM
operation. If the controller enters pulse-skipping opera-
tion, the upper CLKEN and PWRGD threshold remains
blanked. The slew rate (set by resistor R
set fast enough to ensure that the transition may be
completed within the maximum allotted time.
The MAX8770/MAX8771/MAX8772 automatically con-
trol the current to the minimum level required to com-
plete the transition in the calculated time. The slew-rate
controller uses an internal capacitor and current source
programmed by R
The total transition time depends on R
difference, and the accuracy of the slew-rate controller
(C
the total output capacitance, as long as the surge cur-
rent is less than the current limit. For all dynamic VID
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL
SLEW
accuracy). The slew rate is not dependent on
MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-
Output-Voltage Transition Timing
______________________________________________________________________________________
TIME
to transition the output voltage.
TIME
Suspend Mode
TIME
, the voltage
) must be
transitions, the transition time (t
where dV
the slew rate, V
V
Accuracy in Electrical Characteristics for slew-rate lim-
its. For soft-start and shutdown, the controller automati-
cally reduces the slew rate to 1/8.
The output voltage tracks the slewed target voltage,
making the transitions relatively smooth. The average
inductor current per phase required to make an output
voltage transition is:
where dV
the total output capacitance, and η
of active phases.
When DPRSLPVR goes high, the MAX8770/MAX8771/
MAX8772 immediately disable phase 2 (DH2 and DL2
forced low), blank PHASEGD high impedance
(MAX8771 only), and enter pulse-skipping operation
(see Figures 4 and 5). If the VIDs are set to a lower volt-
age setting, the output drops at a rate determined by
the load and the output capacitance. The internal target
still ramps as before, and CLKEN and PWRGD upper
and lower thresholds remain blanked until 20µs after
the internal target reaches the programmed VID code.
Once this time expires, PWRGD monitors only the lower
threshold:
• Fast C4E Deeper Sleep Exit: When exiting deeper
NEW
sleep (DPRSLPVR pulled low) while the output volt-
age still exceeds the deeper sleep voltage, the
MAX8770/MAX8771/MAX8772 quickly slew (50mV/µs
min regardless of R
voltage to the DAC code provided by the processor
as long as the output voltage is above the new tar-
get. The controller remains in skip mode until the out-
put voltage equals the internal target. Once the
internal target reaches the output voltage, phase 2 is
enabled. The controller blanks PWRGD, PHASEGD,
and CLKEN (forced high impedance) until 20µs after
the transition is completed. See Figure 4.
is the new target voltage. See TIME Slew Rate
TARGET
TARGET
I
L
≅
OLD
t
TRAN
/dt is the required slew rate, C
/dt = 12.5mV/µs × 71.5kΩ / R
η
C
TOTAL
OUT
is the original output voltage, and
®
=
TIME
IMVP-6 LICENSEES
(
dV
V
×
NEW
(
TARGET
dV
setting) the internal target
Deeper Sleep Transitions
TARGET
TRAN
−
V
OLD
TOTAL
/
) is given by:
dt
)
/
dt
)
is the number
TIME
OUT
29
is
is