ADE7756ARS Analog Devices Inc, ADE7756ARS Datasheet - Page 16

• Manufacturer Part Number: ADE7756ARS
• Description: IC ENERGY METERING 1PHASE 20SSOP
• Manufacturer: Analog Devices Inc

Specifications of ADE7756ARS

• Rohs Status: RoHS non-compliant
• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 3mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Meter Type: Single Phase
• Lead Free Status / RoHS Status: Not Compliant

ADE7756
TEMPERATURE MEASUREMENT
ADE7756 also includes an on-chip temperature sensor. A tem-
perature measurement can be made by setting Bit 5 in the Mode
register. When Bit 5 is set logic high in the Mode register, the
ADE7756 will initiate a temperature measurement on the next
zero crossing. When the zero crossing on Channel 2 is detected,
the voltage output from the temperature sensing circuit is con-
nected to ADC1 (Channel 1) for digitizing. The resultant code
is processed and placed in the Temperature register (TEMP[7:0])
approximately 26 µs later (24 CLKIN cycles). If enabled in the
Interrupt Enable register (Bit 5), the IRQ output will go active
low when the temperature conversion is finished. Please note
that temperature conversion will introduce a small amount of
noise in the energy calculation. If temperature conversion is
performed frequently (e.g., multiple times per second), a
noticeable error will accumulate in the resulting energy calcu-
lation over time.
The contents of the Temperature register are signed (two’s
complement) with a resolution of approximately 1 LSB/°C. The
temperature register will produce a code of 00h when the ambi-
ent temperature is approximately 70°C—see Figure 13. The
temperature measurement is uncalibrated in the ADE7756 and
has an offset tolerance that could be as high as ± 20°C.
ANALOG-TO-DIGITAL CONVERSION
The analog-to-digital conversion in the ADE7756 is carried out
using two second-order sigma-delta ADCs. The block diagram
in Figure 14 shows a first-order (for simplicity) sigma-delta
ADC. The converter is made up of two parts, first the sigma-
delta modulator and second the digital low-pass filter.
A sigma-delta modulator converts the input signal into a con-
tinuous serial stream of 1s and 0s at a rate determined by the
sampling clock. In the ADE7756 the sampling clock is equal to
CLKIN/4. The 1-bit DAC in the feedback loop is driven by the
serial data stream. The DAC output is subtracted from the input
signal. If the loop gain is high enough, the average value of the
DAC output (and therefore the bit stream) will approach that of
the input signal level. For any given input value in a single
–110
–120
–20
–40
–60
–80
40
20
–60
0
–40
FIVE PARTS
APGAIN = 00h
–20
0
TEMPERATURE– C
20
40
60
80
100
120
sampling interval, the data from the 1-bit ADC is virtually mean-
ingless. Only when a large number of samples are averaged, will
a meaningful result be obtained. This averaging is carried out in
the second part of the ADC, the digital low-pass filter. By aver-
aging a large number of bits from the modulator the low-pass
filter can produce 20-bit data words that are proportional to the
input signal level.
The sigma-delta converter uses two techniques to achieve high
resolution from what is essentially a 1-bit conversion technique.
The first is oversampling. By oversampling we mean that the
signal is sampled at a rate (frequency) that is many times higher
than the bandwidth of interest. For example, the sampling rate
in the ADE7756 is CLKIN/4 (894 kHz) and the band of interest
is 40 Hz to 2 kHz. Oversampling has the effect of spreading
the quantization noise (noise due to sampling) over a wider
bandwidth. With the noise spread more thinly over a wider
bandwidth, the quantization noise in the band of interest is
lowered—see Figure 15. However oversampling alone is not an
efficient enough method to improve the signal to noise ratio
(SNR) in the band of interest. For example, an oversampling
ratio of 4 is required just to increase the SNR by only 6 dB
(1 bit). To keep the oversampling ratio at a reasonable level, it is
possible to shape the quantization noise so that the majority of
the noise lies at the higher frequencies. This is what happens in
the sigma-delta modulator, the noise is shaped by the integrator
which has a high-pass-type response for the quantization noise.
The result is that most of the noise is at the higher frequencies
where it can be removed by the digital low-pass filter. This noise
shaping is also shown in Figure 15.
SIGNAL
SIGNAL
ANALOG LOW-
NOISE
NOISE
PASS FILTER
R
0
0
C
2
2
HIGH RESOLUTION
OUTPUT FROM
DIGITAL LPF
DIGITAL
FILTER
FREQUENCY – kHz
FREQUENCY – kHz
V
REF
INTEGRATOR
FILTER (RC)
1-BIT DAC
ANTIALIAS
447
447
COMPARATOR
LATCHED
10100101
SHAPED
NOISE
MCLK/4
FREQUENCY
SAMPLING
Σ ∆
1
DIGITAL LOW-
PASS FILTER
894
894
20