MT45W4MW16BCGB-701 IT Micron Technology Inc, MT45W4MW16BCGB-701 IT Datasheet - Page 9

• Manufacturer Part Number: MT45W4MW16BCGB-701 IT
• Description: IC PSRAM 64MB 54-VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16BCGB-701 IT

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 64M (4M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q3816748

Table 3:
PDF: 09005aef8247bd51/Source: 09005aef8247bd83
64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN
Mode
Asynchronous
read
Asynchronous
write
Standby
No operation
Initial burst
read
Initial burst
write
Burst
continue
Burst suspend
Configuration
register write
Configuration
register read
DPD
Bus Operations – Burst Mode (BCR[15] = 0)
Deep power-down
Notes:
Standby
Power
Active
Active
Active
Active
Active
Active
Active
Active
Idle
1. CLK must be LOW during asynchronous read and asynchronous write modes and to achieve
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are enabled. When only LB# is in
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally
6. V
7. DPD is initiated when CE# transitions from LOW to HIGH after writing RCR[4] to 0. DPD is
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
9. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the
standby power during standby and DPD modes. CLK must be static (HIGH or LOW) during
burst suspend.
select mode, DQ[7:0] are enabled. When only UB# is in the select mode, DQ[15:8] are
enabled.
isolated from any external influence.
maintained until CE# transitions from HIGH to LOW and is held LOW for
equivalent of a single-word burst (as indicated by WAIT).
IN
= V
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory
CLK
CC
X
L
L
L
L
L
Q or 0V; all device balls must be static (unswitched) to achieve standby current.
1
ADV#
X
X
H
X
X
L
L
L
L
L
L
CE#
H
H
L
L
L
L
L
L
L
L
L
9
OE#
X
X
X
X
H
X
H
H
X
L
L
WE#
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
X
X
H
X
X
H
X
L
L
L
CRE
X
X
H
H
X
L
L
L
L
L
L
LB#/
UB#
X
X
X
X
X
X
L
L
L
L
L
WAIT
High-Z
High-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z Config. reg.
General Description
©2005 Micron Technology, Inc. All rights reserved.
2
DQ[15:0]
Data-in or
Data-out
data-out
Data-in
High-Z
High-Z
High-Z
High-Z
t
DPDX.
out
X
X
X
3
Notes
5, 6
4, 6
4, 8
4, 8
4, 8
4, 8
8, 9
8, 9
4
4
7