MT45W4MW16BCGB-701 IT Micron Technology Inc, MT45W4MW16BCGB-701 IT Datasheet - Page 13

• Manufacturer Part Number: MT45W4MW16BCGB-701 IT
• Description: IC PSRAM 64MB 54-VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16BCGB-701 IT

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 64M (4M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q3816748

Page Mode READ Operation
Figure 7:
Burst Mode Operation
PDF: 09005aef8247bd51/Source: 09005aef8247bd83
64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN
Page Mode READ Operation (ADV# LOW)
Page mode is a performance-enhancing extension to the legacy asynchronous READ
operation. In page-mode-capable products, an initial asynchronous read access is
performed, and then adjacent addresses can be read quickly by simply changing the
low-order address. Addresses A[3:0] are used to determine the members of the 16-
address CellularRAM page. Any change in addresses A[4] or higher will initiate a new
access time. Figure 7 shows the timing for a page mode access. Page mode takes advan-
tage of the fact that adjacent addresses can be read in a shorter period of time than
random addresses. WRITE operations do not include comparable page mode function-
ality.
During asynchronous page mode operation, the CLK input must be held LOW. CE# must
be driven HIGH upon completion of a page mode access. WAIT will be driven while the
device is enabled, and its state should be ignored. Page mode is enabled by setting
RCR[7] to HIGH. ADV must be driven LOW during all page mode read accesses.
Due to refresh considerations, CE# must not remain LOW longer than
LB#/UB#
Burst mode operations enable high-speed synchronous READ and WRITE operations.
Burst operations consist of a multiclock sequence that must be performed in an ordered
fashion. After CE# goes LOW, the address to access is latched on the rising edge of the
next clock that ADV# is LOW. During this first clock rising edge, WE# indicates whether
the operation is going to be a READ (WE# = HIGH, Figure 8 on page 14) or a WRITE
(WE# = LOW, Figure 9 on page 15).
The size of a burst can be specified in the BCR either as a fixed-length or continuous.
Fixed-length bursts consist of 4, 8, 16, or 32 words. Continuous bursts have the ability to
start at a specified address and burst to the end of the 128-word row.
The latency count stored in the BCR defines the number of clock cycles that elapse
before the initial data value is transferred between the processor and the CellularRAM
device. The initial latency for READ operations can be configured as fixed or variable
Address
Data
WE#
OE#
CE#
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
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©2005 Micron Technology, Inc. All rights reserved.
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