MT45W4MW16BCGB-701 IT Micron Technology Inc, MT45W4MW16BCGB-701 IT Datasheet - Page 61

• Manufacturer Part Number: MT45W4MW16BCGB-701 IT
• Description: IC PSRAM 64MB 54-VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16BCGB-701 IT

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 64M (4M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q3816748

Figure 48:
PDF: 09005aef8247bd51/Source: 09005aef8247bd83
64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN
2nd cycle WRITE
2nd cycle WRITE
2nd cycle WRITE
DQ[15:0] IN
LB#/UB#
A[21:0]
ADV#
WAIT
WE#
OE#
CLK
CE#
Burst WRITE Interrupted by Burst WRITE or READ – Variable Latency Mode
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
OH
OL
IH
IL
IH
IL
IH
IL
Notes:
High-Z
t CSP
t SP
t SP
t SP
address
1. Nondefault BCR settings for burst WRITE interrupted by burst WRITE or READ in variable
2. Burst interrupt shown on first allowable clock (such as after first data word written).
3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than
Valid
t HD
t HD
t HD
latency mode: fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT
asserted during delay. All bursts shown for variable latency; no refresh collision.
t
High-Z
CEM.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory
2nd cycle READ
2nd cycle READ
2nd cycle READ
DQ[15:0] OUT
t CLK
LB#/UB#
OE#
t SP
t SP t HD
D0
t HD
V
V
V
V
V
V
IH
IL
IH
IL
OH
OL
t CEW
t HD
t SP
t SP
t SP t HD
address
address
t SP
Valid
Valid
61
t KHTL
t HD
WRITE burst interrupted with new WRITE or READ. See Note 2.
V
V
OH
OL
Micron Technology, Inc., reserves the right to change products or specifications without notice.
High-Z
t CEM (Note 3)
t BOE
t ACLK
t SP
output
Valid
D0
t KOH
t HD
output
D1
Valid
Don’t Care
©2005 Micron Technology, Inc. All rights reserved.
output
Timing Diagrams
D2
Valid
D3
output
Valid
t HD
t HD
t OHZ
Undefined
High-Z