CYD09S18V18-167BBXI Cypress Semiconductor Corp, CYD09S18V18-167BBXI Datasheet - Page 2

IC SRAM 9MBIT 167MHZ 256LFBGA

CYD09S18V18-167BBXI

Manufacturer Part Number
CYD09S18V18-167BBXI
Description
IC SRAM 9MBIT 167MHZ 256LFBGA
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CYD09S18V18-167BBXI

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
9M (512K x 18)
Speed
167MHz
Interface
Parallel
Voltage - Supply
1.42 V ~ 1.58 V, 1.7 V ~ 1.9 V
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CYD09S18V18-167BBXI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
135
Part Number:
CYD09S18V18-167BBXI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Logic Block Diagram
The Logic Block Diagram for FullFlex72, FullFlex36, and FullFlex18 family follows:
Notes
Document Number: 38-06082 Rev. *J
1. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and
2. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines.
3. The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte enables.
CYD09S18V18 devices have 19 address bits. The CYD18S72V18, CYD09S36V18, and CYD04S18V18 devices have 18 address bits. The CYD09S72V18 and
CYD04S36V18 devices have 17 address bits. The CYD04S72V18 and CYD02S36V18 have 16 address bits.
PORTSTD[1:0]
CNT/
CNTRST
CNTINT
CNTEN
A [20:0]
DQ[71:0]
ADS
WRP
FTSEL
RET
BE
CQEN
C
R/
CQ1
CQ1
CQ0
CQ0
CE1
CE
OE
MSK
L
INT
W
[7:0]
L
L
L
0
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
BUSY
Counter Logic
CONFIG Block
Mailboxes
Address &
L
Control
IO
LowSPD
Dual Port Array
READY
ZQ1
Collision Detection Logic
ZQ0
L
L
L
L
INT
R
Counter Logic
CONFIG Block
Address &
RESET
LOGIC
JTAG
Control
[1, 2, 3]
IO
BUSY
R
CNT/
CNTRST
CNTINT
PORTSTD[1:0]
A [20:0]
CNTEN
READY
TRST
LowSPD
DQ [71:0]
MRST
ADS
RET
WRP
TMS
TDO
TCK
BE
TDI
ZQ1
ZQ0
FTSEL
CQEN
C
R/
CQ1
CQ0
CQ1
CQ0
CE
OE
CE1
MSK
R
[7:0]
W
R
R
R
R
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
FullFlex
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