MAX9257AGCM+ Maxim Integrated, MAX9257AGCM+ Datasheet - Page 35

• Manufacturer Part Number: MAX9257AGCM+
• Description: Serializers & Deserializers - Serdes Prog Serializer / Deserializer
• Manufacturer: Maxim Integrated
• Type: Serializerr

Specifications of MAX9257AGCM+

• Rohs: yes
• Data Rate: 840 Mbit/s
• Input Type: LVCMOS
• Output Type: LVDS
• Number Of Inputs: 18
• Number Of Outputs: 1
• Operating Supply Voltage: 1.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V, 3 V

During the PRBS test, the MAX9258A checks received
PRBS data words by comparing them to internally gener-
ated PRBS data. Detected errors are counted in the PRBS
error register (REG12) in the MAX9258A. Whenever the
number of detected PRBS errors is more than 0, ERROR
asserts low. The PRBS error register is reset when ECU
writes a 0 to PRBSEN register (REG4[0]). In this case,
ERROR deasserts high immediately if PRBS errors were
the only reason that ERROR was asserted low.
The short synchronization pattern is part of the handshak-
ing procedure between the MAX9257A and MAX9258A
after the control channel phase. It is used to resynchro-
nize the MAX9258A’s clock and data recovery circuit
to the MAX9257A before the video phase begins. The
MAX9257A transmits the short synchronization pattern
when it receives the lock frame from the MAX9258A. The
length of short synchronization pattern is dependant on
the PRATE range. When PRATE is 00 or 01, the short
synchroniza tion pattern consists of 546 words and when
PRATE is 10 or 11, the short synchronization pattern con-
sists of 1090 words. Every word is one pixel clock period.
At power-up or when the MAX9257A does not receive a
lock frame from the MAX9258A, the MAX9257A transmits
a long synchronization pattern. The long synchronization
pattern consists of 17,410 words. Every word is one pixel
clock period. When REM is high, if synchroniza tion is not
achieved after 62 attempts, the MAX9257A resets SEREN
to 0 so that the control channel stays open to allow trou-
bleshooting. When REM is low, the MAX9257A/MAX9258A
continuously tries to reestablish the connection.
At the end of every vertical blanking time, the MAX9257A
verifies that the MAX9258A did not lose lock. The
MAX9258A handshakes with the MAX9257A to indicate
lock status. The handshaking occurs after the channel
closes
errors in a time window did not exceed a certain thresh-
old during the last video phase, the MAX9258A sends
back the lock frame that indicates lock. If the MAX9257A
receives the lock frame, the MAX9257A transmits a short
synchronization pattern. The MAX9258A features a pro-
prietary VCO mechanism that prevents frequency drift
while in the control channel. This allows for successful
resynchronization after extended use of control chan-
nel. If the number of decoding errors in a time window
(Figures 28
Lock Verification (Handshaking)
���������������������������������������������������������������� Maxim Integrated Products 35
Short Synchronization Pattern
Long Synchronization Pattern
and 23). If the number of decoding
Fully Programmable Serializer/Deserializer
PRBS Errors
with UART/I
Table 27. Link Status
exceeds a certain threshold, the MAX9258A loses lock,
LOCK goes low, and the lock frame is not sent. The
MAX9258A also loses lock if handshaking is not suc-
cessful. If the MAX9257A does not receive the lock frame,
it transmits a long synchronization pattern before the start
of next video phase. When REM = 1, if the lock frame
is not received by the MAX9257A after 62 consec utive
attempts to synchronize, SEREN is disabled so that the
control channel opens permanently for trou bleshooting.
The LOCK output indicates whether the MAX9258A is
locked to the MAX9257A. LOCK is an open-drain out-
put that needs to be pulled up to V
low to indicate that the MAX9258A is not locked to the
MAX9257A and high when it is. In the control channel
phase, LOCK stays high if LOCK is high in the video
phase. While in the control channel phase, the MAX9258A
PLL frequency is held constant, PCLK output is active
and data outputs are frozen at their last valid value before
entering the control channel. CCEN output indicates
whether the devices are in the control channel phase
or video phase. CCEN goes high when the devices are
in the control channel phase
power-up, CCEN goes high before communication in the
control channel is ready (see the
The control channel is used by the ECU to program
registers in the MAX9257A, MAX9258A, and peripheral
devices (such as a camera) during vertical blanking, after
power-up, or when serialization is disabled. Control chan-
nel communication is half-duplex UART. The peripheral
interface on the MAX9257A can be pro grammed to be I
or UART. Operation of the control channel is synchronized
with the VSYNC input after the ECU starts serialization of
video data. Programmable timers, ECU signal activity,
and end frame determine how long the control channel
stays open. The control channel remains open as long
as there is signal activity from the ECU. When the control
channel closes, the LVDS serial link is reestablished.
LOCK
MAX9257A/MAX9258A
1
1
0
2
C Control Channel
Overview of Control Channel Operation
Link Status (LOCK and CCEN)
CCEN
0
1
X
LVDS channel active
Control channel active
PLL loss of lock
(Table
Link Power-Up
Control Channel
INDICATION
CC
27). Only at initial
. LOCK asserts
section).
2
C