MAX9257AGCM+ Maxim Integrated, MAX9257AGCM+ Datasheet - Page 12

• Manufacturer Part Number: MAX9257AGCM+
• Description: Serializers & Deserializers - Serdes Prog Serializer / Deserializer
• Manufacturer: Maxim Integrated
• Type: Serializerr

Specifications of MAX9257AGCM+

• Rohs: yes
• Data Rate: 840 Mbit/s
• Input Type: LVCMOS
• Output Type: LVDS
• Number Of Inputs: 18
• Number Of Outputs: 1
• Operating Supply Voltage: 1.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V, 3 V

19, 34
20, 33
TQFN
2, 11,
1, 18
3–8
10
12
13
14
15
16
17
21
22
23
24
25
26
27
28
9
PIN
22, 41
23, 40
LQFP
3, 14,
2, 21
4–9
10
11
15
16
17
18
19
20
26
27
28
29
30
31
32
33
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Fully Programmable Serializer/Deserializer
DIN15/GPIO7
HSYNC_IN
VSYNC_IN
GNDLVDS
DIN[9:14]/
GPIO[1:6]
GNDFPLL
GNDSPLL
PCLK_IN
V
V
V
SDA/RX
SCL/TX
V CCIO
NAME
GPIO8
GPIO9
CCLVDS
CCFPLL
CCSPLL
SDO+
SDO-
GND
V
CC
Single-Ended Input/Output Buffer Supply Voltage. Bypass V CCIO to GND with 0.1FF and
0.001FF capacitors in parallel as close as possible to the device with the smallest value
capacitor closest to V CCIO .
Digital Supply Ground
Data Input/General Purpose Input/Output. When a serial-data word is less than 18 bits word
length, DIN_ not programmed as data inputs becomes GPIO (Table 22). DIN[9:14] are inter-
nally pulled down to ground.
Filter PLL Ground
Filter PLL Supply Voltage. Bypass V
in parallel as close as possible to the device with the smallest value capacitor closest to
V
Data Input/General Purpose Input/Output. When a serial-data word is less than 18 bits word
length, DIN_ not programmed as data input becomes GPIO (Table 22). DIN15 is internally
pulled down to ground.
Horizontal SYNC Input. HSYNC_IN is internally pulled down to ground.
Vertical SYNC Input. VSYNC_IN is internally pulled down to ground.
Parallel Clock Input. PCLK_IN latches data and sync inputs and provides the PLL reference
clock. PCLK_IN is internally pulled down to ground.
Open-Drain Control Channel Output. SCL/TX becomes SCL output when UART-to-I
SCL/TX becomes TX output when UART-to-I
Open-Drain Control Channel Input/Output. SDA/RX becomes bidirectional SDA when UART-
to-I 2 C is active. SDA/RX becomes RX input when UART-to-I
requires a pullup to V
Digital Supply Voltage. Bypass V CC to ground with 0.1FF and 0.001FF capacitors in parallel
as close as possible to the device with the smallest value capacitor closest to V
General Purpose Input/Output
General Purpose Input/Output
Spread PLL Supply Voltage. Bypass V
tors in parallel as close as possible to the device with the smallest value capacitor closest to
V
SPLL Ground
LVDS Ground
Serial LVDS Inverting Output
Serial LVDS Noninverting Output
LVDS Supply Voltage. Bypass V
in parallel as close as possible to the device with the smallest value capacitor closest to
V
CCFPLL
CCSPLL
CCLVDS
.
.
.
with UART/I
CC
.
CCLVDS
CCFPLL
MAX9257A/MAX9258A
CCSPLL
to GNDLVDS with 0.1FF and 0.001FF capacitors
FUNCTION
2
to GNDFPLL with 0.1FF and 0.001FF capacitors
C is bypassed. Externally pull up to V
2
MAX9257A Pin Description
to GNDSPLL with 0.1FF and 0.001FF capaci-
C Control Channel
2
C is bypassed. SDA output
CC
.
CC
2
C is active.
.