MAX9257AGCM+ Maxim Integrated, MAX9257AGCM+ Datasheet - Page 21

• Manufacturer Part Number: MAX9257AGCM+
• Description: Serializers & Deserializers - Serdes Prog Serializer / Deserializer
• Manufacturer: Maxim Integrated
• Type: Serializerr

Specifications of MAX9257AGCM+

• Rohs: yes
• Data Rate: 840 Mbit/s
• Input Type: LVCMOS
• Output Type: LVDS
• Number Of Inputs: 18
• Number Of Outputs: 1
• Operating Supply Voltage: 1.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V, 3 V

The MAX9257A serializer pairs with the MAX9258A
deseri alizer to form a complete digital video serial link.
The electronic control unit (ECU) programs the registers
in the MAX9257A, MAX9258A, and peripheral devices,
such as a camera, during the control channel phase that
occurs at startup or during the vertical blanking time.
All control channel communication is half-duplex. The
UART communication between the MAX9258A and the
MAX9257A is encoded to allow transmission through
AC-coupling capacitors. The MAX9257A communicates
to the peripheral device through UART or I
Figure 19. Video and Control Channel Phases (Spread Off)
Figure 20. Video and Control Channel Phases (MAX9257A Spread is Enabled)
VSYNC_IN
VSYNC_IN
PROFILE
SPREAD
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SDI/O
SDI/O
SDI/O
SDI/O
CCEN
CCEN
Fully Programmable Serializer/Deserializer
Detailed Description
VIDEO
VIDEO
0.5/f
8t
(max)
T
SSM
2
C.
with UART/I
HSK = HANDSHAKING
HSK = HANDSHAKING
CONTROL
CONTROL
The MAX9257A/MAX9258A DC-balanced serializer and
deserializer operate from a 5MHz-to-70MHz parallel
clock frequency, and are capable of serializing and
deserializing programmable 10, 12, 14, 16, and 18
bits parallel data during the video phase. The devices
have two phases of operation: video and control chan-
nel
MAX9257A accepts parallel video data and transmits
serial encoded data over the LVDS link. The MAX9258A
accepts the encoded serial LVDS data and converts
it back to parallel output data. The MAX9257A has
dedicated inputs for HSYNC and VSYNC. The selected
VSYNC edge causes the MAX9257A/MAX9258A to enter
the control channel phase. Nonactive VSYNC edge can
be asserted after eight pixel clock cycles.
(Figure 19
MAX9257A/MAX9258A
2
C Control Channel
and 20). During the video phase, the
HSK
HSK
VIDEO
VIDEO