MAX9257AGCM+ Maxim Integrated, MAX9257AGCM+ Datasheet - Page 22

• Manufacturer Part Number: MAX9257AGCM+
• Description: Serializers & Deserializers - Serdes Prog Serializer / Deserializer
• Manufacturer: Maxim Integrated
• Type: Serializerr

Specifications of MAX9257AGCM+

• Rohs: yes
• Data Rate: 840 Mbit/s
• Input Type: LVCMOS
• Output Type: LVDS
• Number Of Inputs: 18
• Number Of Outputs: 1
• Operating Supply Voltage: 1.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V, 3 V

The video data are coded using two overhead bits (EN0
and EN1) resulting in a serial-word length of N+2 bits.
The devices feature programmable parity encoding that
adds two parity bits to the serial word. Bit 0 (EN0) is the
LSB that is serialized first with out parity enabled. The par-
ity bits are serialized first when parity is enabled.
The ECU programs the MAX9258A, MAX9257A, and
peripheral devices at startup and during the control
channel phase. In a digital video system, the control
channel phase occurs during the vertical blanking time
and synchronizes to the VSYNC signal. The programma-
ble active edge of VSYNC initiates the control channel
phase. Nonactive edge of VSYNC can transition at any
time after 8 x t
0.5/f
MAX9258A drives CCEN high to indicate to the ECU
Table 1. MAX9257A Power-Up Default Register Map (see the MAX9257A Register Table)
REGISTER NAME
SSM
REG0
REG1
REG2
REG3
REG4
when enabled. At the end of video phase, the
T
if MAX9257A spread is not enabled and
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Fully Programmable Serializer/Deserializer
ADDRESS (hex)
REGISTER
0x00
0x01
0x02
0x03
0x04
POWER-UP VALUE
1) REM = 0, 0x28
2) REM = 1, 0x30
with UART/I
(hex)
0xB5
0xA0
0xA0
0x1F
PRATE = 10, 20MHz to 40MHz
SRATE = 11, 400Mbps to 840Mbps
PAREN = 0, parity disabled
PWIDTH = 101, parallel data width = 18
SPREAD = 000, spread = off
Reserved = 11111
STODIV = 1010, STO clock is pixel clock divided by 1024
STOCNT = 0000, STO counter counts to 1
ETODIV = 1010, ETO clock is pixel clock divided by 1024
ETOCNT = 0000, ETO counter counts to 1
VEDGE = 0, VSYNC active edge is falling
Reserved = 0
CKEDGE = 1, pixel clock active edge is rising
SEREN: 1) If REM = 0, SEREN = 1
BYPFPLL = 0, filter PLL is active
Reserved = 0
PRBSEN = 0, PRBS test disabled
that the control channel is open. Programmable timers
and ECU signal activity determine how long the control
channel stays open. The timers are reset by ECU signal
activity. ECU programming must not exceed the vertical
blanking time to avoid loss of video data.
After the control channel phase closes, the MAX9257A
sends a 546 or 1090 word pattern as handshaking (HSK)
to synchronize the MAX9258A’s internal clock recovery
circuit to the MAX9257A’s transmitted data. Following
the handshaking, the control channel is closed and the
video phase begins. The serial LVDS data is recovered
and parallel data is valid on the pro grammed edge of the
recovered pixel clock.
Table 1
MAX9257A/MAX9258A registers.
the input and output supply references.
PD: 1) If REM = 0, PD = 0
2) If REM = 1, PD = 1
2) If REM = 1, SEREN = 0
MAX9257A/MAX9258A
and
POWER-UP DEFAULT SETTINGS
2
2
C Control Channel
show the default power-up values for the
Tables 3
and
4
show