C8051F961-A-GM Silicon Labs, C8051F961-A-GM Datasheet - Page 462

• Manufacturer Part Number: C8051F961-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, LCD AES, QFN40
• Manufacturer: Silicon Labs

Specifications of C8051F961-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-40
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 34
• Number Of Timers: 4

C8051F96x
Setting TF3CEN to 1 enables the SmaRTClock/External Oscillator Capture Mode for Timer 3. In this mode,
T3SPLIT should be set to 0, as the full 16-bit timer is used.
When Capture Mode is enabled, a capture event will be generated either every SmaRTClock rising edge
or every 8 external clock cycles, depending on the T3XCLK1 setting. When the capture event occurs, the
contents of Timer 3 (TMR3H:TMR3L) are loaded into the Timer 3 reload registers (TMR3RLH:TMR3RLL)
and the TF3H flag is set (triggering an interrupt if Timer 3 interrupts are enabled). By recording the differ-
ence between two successive timer capture values, the SmaRTClock or external clock period can be
determined with respect to the Timer 3 clock. The Timer 3 clock should be much faster than the capture
clock to achieve an accurate reading.
For example, if T3ML = 1b, T3XCLK1 = 0b, and TF3CEN = 1b, Timer 3 will clock every SYSCLK and cap-
ture every SmaRTClock rising edge. If SYSCLK is 24.5 MHz and the difference between two successive
captures is 350 counts, then the SmaRTClock period is as follows:
350 x (1 / 24.5 MHz) = 14.2 µs.
This mode allows software to determine the exact frequency of the external oscillator in C and RC mode or
the time between consecutive SmaRTClock rising edges, which is useful for determining the SmaRTClock
frequency.
462
E xtern al C lock/8
E xte rna l C lock/8
S m a R T C lo ck
S Y S C LK /12
S m aR T C loc k
S Y S C LK
T 3X C L K [1:0]
T 3X C L K 1
X 0
01
11
1
0
Figure 32.9. Timer 3 Capture Mode Block Diagram
M
T
H
3
M
T
3
L
0
1
C K C O N
M
H
T
2
M
T
2
L
M
T
1
T F 3 C E N
M
T
0
S
C
A
1
T R 3
C
S
A
0
Rev. 0.5
C ap ture
T C L K
T M R 3R LL T M R 3 R LH
T M R 3L
T M R 3 H
T 3X C L K 1
T 3X C L K 0
T F 3 C E N
T 3 S P LIT
T F 3 L E N
T F 3H
T F 3 L
T R 3
Interrupt