C8051F961-A-GM Silicon Labs, C8051F961-A-GM Datasheet - Page 397

• Manufacturer Part Number: C8051F961-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, LCD AES, QFN40
• Manufacturer: Silicon Labs

Specifications of C8051F961-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-40
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 34
• Number Of Timers: 4

28.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. The appropriate actions to
take in response to an SMBus event depend on whether hardware slave address recognition and ACK
generation is enabled or disabled. Table 28.5 describes the typical actions when hardware slave address
recognition and ACK generation is disabled. Table 28.6 describes the typical actions when hardware slave
address recognition and ACK generation is enabled. In the tables, STATUS VECTOR refers to the four
upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options are only the typ-
ical responses; application-specific procedures are allowed as long as they conform to the SMBus specifi-
cation. Highlighted responses are allowed by hardware but do not conform to the SMBus specification.
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
Figure 28.8. Typical Slave Read Sequence
R
A
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
Data Byte
Rev. 0.5
A
S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address
Data Byte
N
C8051F96x
P
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