C8051F961-A-GM Silicon Labs, C8051F961-A-GM Datasheet - Page 346

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C8051F961-A-GM

Manufacturer Part Number
C8051F961-A-GM
Description
8-bit Microcontrollers - MCU 128KB, DC-DC, LCD AES, QFN40
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F961-A-GM

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
128 KB
Data Ram Size
8448 B
On-chip Adc
Yes
Operating Supply Voltage
2.5 V to 3.3 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFN-40
Mounting Style
SMD/SMT
Number Of Programmable I/os
34
Number Of Timers
4
C8051F96x
26.6. Blinking LCD Segments
The LCD driver supports blinking LCD applications such as clock applications where the “:” separator tog-
gles on and off once per second. If the LCD is only displaying the hours and minutes, then the device only
needs to wake up once per minute to update the display. The once per second blinking is automatically
handled by the C8051F96x.
The LCD0BLINK register can be used to enable blinking on any LCD segment connected to the LCD0 or
LCD1 segment pin. In static mode, a maximum of 2 segments can blink. In 2-mux mode, a maximum of 4
segments can blink; in 3-mux mode, a maximum of 6 segments can blink; and in 4-mux mode, a maximum
of 8 segments can blink. The LCD0BLINK mask register targets the same LCD segments as the LCD0D0
register. If an LCD0BLINK bit corresponding to an LCD segment is set to 1, then that segment will toggle at
the frequency set by the LCD0TOGR register without any software intervention.
SFR Definition 26.10. LCD0BLINK: LCD0 Blink Mask
SFR Page = 0x2; SFR Address = 0x9E
346
Name
Reset
Type
7:0
Bit
Bit
LCD0BLINK[7:0] LCD0 Blink Mask.
R/W
7
0
Name
R/W
6
0
Each bit maps to a specific LCD segment connected to the LCD0 and LCD1
segment pins. A value of 1 indicates that the segment is blinking. A value of 0
indicates that the segment is not blinking. This bit to segment mapping is the
same as the LCD0D0 register.
R/W
5
0
R/W
LCD0BLINK[7:0]
Rev. 0.5
4
0
R/W
3
0
Function
R/W
2
0
R/W
1
0
R/W
0
0

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