EDD1216AATA-5 ELPIDA [Elpida Memory], EDD1216AATA-5 Datasheet - Page 7

• Manufacturer Part Number: EDD1216AATA-5
• Description: 128M bits DDR SDRAM (8M words x 16 bits, DDR400)
• Manufacturer: ELPIDA [Elpida Memory]

Parameter
Mode register set command cycle time
Active to Precharge command period
Active to Active/Auto refresh command
period
Auto refresh to Active/Auto refresh
command period
Active to Read/Write delay
Precharge to active command period
Active to Autoprecharge delay
Active to active command period
Write recovery time
Auto precharge write recovery and
precharge time
Internal write to Read command delay
Average periodic refresh interval
Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter
Data Sheet E0443E40 (Ver. 4.0)
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
7. Input valid windows is defined to be the period between two successive transition of data input or DQS
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these
12. VDD is assumed to be 2.6V ± 0.1V. VDD power supply variation per cycle expected to be less than
13. tDAL = (tWR/tCK)+(tRP/tCK)
definitions, see ‘Timing Waveforms’ section.
transition is defined to occur when the signal level crossing VTT.
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.
reference voltage to judge this transition is not given.
assured.
values are 10% of tCK.
0.4V/400 cycle.
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For –5C Speed at CL = 3, tCK = 5ns, tWR = 15ns and tRP= 18ns,
tDAL = (15ns/5ns) + (18ns/5ns) = (3) + (4)
tDAL = 7 clocks
Symbol
tMRD
tRAS
tRC
tRFC
tRCD
tRP
tRAP
tRRD
tWR
tDAL
tWTR
tREF
-5B
min.
2
40
55
70
15
15
tRCD min.
10
15
(tWR/tCK)+
(tRP/tCK)
2
—
7
max.
—
120000
—
—
—
—
—
—
—
—
15.6
—
2
40
-5C
min.
60
70
18
18
tRCD min.
10
15
(tWR/tCK)+
(tRP/tCK)
2
—
max.
—
120000
—
—
—
—
—
—
—
—
—
15.6
EDD1216AATA-5
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
µs
Notes
13