EDD1216AATA-5 ELPIDA [Elpida Memory], EDD1216AATA-5 Datasheet - Page 21

• Manufacturer Part Number: EDD1216AATA-5
• Description: 128M bits DDR SDRAM (8M words x 16 bits, DDR400)
• Manufacturer: ELPIDA [Elpida Memory]

Operation of the DDR SDRAM
Power-up Sequence
(2) Start clock and maintain stable condition for a minimum of 200 µs.
(3) After the minimum 200 µs of stable power and clock (CK, /CK), apply NOP and take CKE high.
(4) Issue precharge all command for the device.
(5) Issue EMRS to enable DLL.
(6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200 cycles of
(7) Issue precharge all command for the device.
(8) Issue 2 or more auto-refresh commands.
(9) Issue a mode register set command to initialize device operation with bit A8 set to low in order to avoid resetting
Mode Register and Extended Mode Register Set
There are two mode registers, the mode register and the extended mode register so as to define the operating
mode. Parameters are set to both through the A0 to the A11 and BA0, BA1 pins by the mode register set command
[MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode register are
set by inputting signal via the A0 to the A11 and BA0, BA1 during mode register set cycles. BA0 and BA1 determine
which one of the mode register or the extended mode register are set. Prior to a read or a write operation, the mode
register must be set.
Remind that no other parameters shown in the table bellow are allowed to input to the registers.
Data Sheet E0443E40 (Ver. 4.0)
(1) Apply power and maintain CKE at an LVCMOS low state (all other inputs are undefined).
Command
Apply VDD before or at the same time as VDDQ.
Apply VDDQ before or at the same time as VTT and VREF.
clock input is required to lock the DLL after every DLL reset).
the DLL.
/CK
CK
PALL
(4)
BA0
0
2 cycles (min.)
MRS
A8
0 No
1 Yes
BA1
DLL Reset
0
DLL enable
EMRS
(5)
A11 A10
2 cycles (min.)
0
0
A6 A5 A4 CAS Latency
DLL reset with A8 = High
Mode Register Set [MRS] (BA0 = 0, BA1 = 0)
0
Power-up Sequence after CKE Goes High
(6)
MRS
2 cycles (min.)
1
A9
0
1
DR
A8
PALL
(7)
A7
0
3
A6
t
21
RP
LMODE
200 cycles (min)
A5
A3
0 Sequential
1 Interleave
REF
Burst Type
A4
REF
(8)
t
A3
BT
RFC
REF
A2 A1 A0
0
0
0
A2
0
1
1
t
RFC
A1
BL
Disable DLL reset with A8 = Low
1
0
1
EDD1216AATA-5
MRS
(9)
Burst Length
BT=0 BT=1
A0
2
4
8
2 cycles (min.)
2
4
8
command
Any