932S208YFLNT IDT [Integrated Device Technology], 932S208YFLNT Datasheet - Page 3

• Manufacturer Part Number: 932S208YFLNT
• Description: Programmable Timing Control HubTM for Next Gen P4TM Processor
• Manufacturer: IDT [Integrated Device Technology]

Pin Description (continued)
IDT
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
PIN #
ICS932S208
Programmable Timing Control Hub
TM
Programmable Timing Control Hub
3V66_4/VCH
SDATA
48MHz_USB
48MHz_DOT
GND
VDD48
Vtt_PWRGD#
VDD
SRCCLKC
SRCCLKT
GND
CPUCLKC0
CPUCLKT0
VDDCPU
CPUCLKC1
CPUCLKT1
GND
CPUCLKC2
CPUCLKT2
VDDCPU
CPUCLKC3
CPUCLKT3
FS_A
IREF
GND
GNDA
VDDA
FS_B
PIN NAME
TM
OUT
PWR
IN
OUT
OUT
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
IN
OUT
PWR
PWR
I/O
OUT
OUT
PWR
PWR
PWR
PWR
PWR
IN
PIN TYPE
for Next Gen P4
TM
for Next Gen P4
66.66MHz clock output for AGP support. AGP-PCI should be aligned
with a skew window tolerance of 500ps.
VCH is 48MHz clock output for video controller hub.
Data pin for I2C circuitry 5V tolerant
48MHz clock output.
48MHz clock output.
Ground pin.
Power pin for the 48MHz output.3.3V
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
Power supply for SRC clocks, nominal 3.3V
Complement clock of differential pair for S-ATA support.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Frequency select pin, see Frequency table for functionality
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin.
Ground pin for core.
3.3V power for the PLL core.
Frequency select pin, see Frequency table for functionality
+/- 300ppm accuracy required.
TM
Processor
TM
Processor
3
DESCRIPTION
0743G—01/26/10