IC42S16100-5T ICSI [Integrated Circuit Solution Inc], IC42S16100-5T Datasheet - Page 32

• Manufacturer Part Number: IC42S16100-5T
• Description: 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
• Manufacturer: ICSI [Integrated Circuit Solution Inc]

IC42S16100
32
Read Cycle (Full Page) Interruption Using
The IC42S16100 can output data continuously from the
burst start address (a) to location a+255 during a read
cycle in which the burst length is set to full page. The
IC42S16100 repeats the operation starting at the 256th
cycle with the data output returning to location (a) and
continuing with a+1, a+2, a+3, etc. A burst stop command
must be executed to terminate this cycle. A precharge
command must be executed within the ACT to PRE
command period (t
command.
CAS latency = 2, burst length = full page
CAS latency = 3, burst length = full page
the Burst Stop Command
COMMAND
COMMAND
CLK
CLK
I/O
I/O
READ (CA=A, BANK 0)
RAS
READ (CA=A, BANK 0)
READ A0
READ A0
max.) following the burst stop
D
OUT
A0
D
D
OUT
OUT
A0
A0
After the period (t
following the execution of the burst stop command has
elapsed, the outputs go to the HIGH impedance state. This
period (t
and three clock cycle when the CAS latency is three.
D
D
OUT
OUT
CAS
CAS
CAS
CAS
CAS Latency
RBD
A1
A0
t
RBD
) is two clock cycle when the CAS latency is two
BURST STOP
BURST STOP
D
D
OUT
BST
OUT
BST
RBD
A2
A1
) required for burst data output to stop
t
Integrated Circuit Solution Inc.
RBD
D
D
OUT
OUT
t
RBD
A3
A2
3
3
D
OUT
HI-Z
DR024-0D 06/25/2004
A3
2
2
HI-Z