IS41C16256-25K ICSI [Integrated Circuit Solution Inc], IS41C16256-25K Datasheet

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IS41C16256-25K

Manufacturer Part Number
IS41C16256-25K
Description
256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
Manufacturer
ICSI [Integrated Circuit Solution Inc]
Datasheet
PIN CONFIGURATIONS
40-Pin TSOP-2
IS41C16256
IS41LV16256
256K x 16 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
FEATURES
• Extended Data-Out (EDO) Page Mode access cycle
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval: 512 cycles /8 ms
• Refresh Mode: RAS-Only, CAS-before-RAS (CBR),
• Single power supply:
• Byte Write and Byte Read operation via two CAS
• Industrial Temperature Range -40
KEY TIMING PARAMETERS
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR001-0E 01/25/2002
Hidden
Parameter
Max. RAS Access Time (t
Max. CAS Access Time (t
Max. Column Address Access Time (t
Min. EDO Page Mode Cycle Time (t
Min. Read/Write Cycle Time (t
VCC
VCC
VCC
RAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
5V ± 10% (IS41C16256)
3.3V ± 10% (IS41LV16256)
WE
NC
NC
NC
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RAC
CAC
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
)
)
RC
)
PC
o
AA
)
C to 85
40-Pin SOJ
)
VCC
VCC
RAS
VCC
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
WE
NC
NC
NC
A0
A1
A2
A3
o
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
-25(5V)
25
10
12
10
45
DESCRIPTION
The
bit high-performance CMOS Dynamic Random Access Memo-
ries. The IS41C16256 offer an accelerated cycle access
called EDO Page Mode. EDO Page Mode allows 512 random
accesses within a single row with access cycle time as short
as 10 ns per 16-bit word. The Byte Write control, of upper and
lower byte, makes the IS41C16256 ideal for use in
16-, 32-bit wide data bus systems.
These features make the IS41C16256and IS41LV16256 ideally
suited for high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.
The IS41C16256 is packaged in a 40-pin 400mil SOJ and
400mil TSOP-2.
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
ICSI
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
-35
35
10
18
12
60
IS41C16256 and IS41LV16256 is a 262,144 x 16-
PIN DESCRIPTIONS
I/O0-15
A0-A8
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
-50
50
14
25
20
90
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
Ground
No Connection
-60
110
60
15
30
25
Unit
ns
ns
ns
ns
ns
1

Related parts for IS41C16256-25K

IS41C16256-25K Summary of contents

Page 1

... These features make the IS41C16256and IS41LV16256 ideally suited for high-bandwidth graphics, digital signal processing high-performance computing systems, and peripheral applications. The IS41C16256 is packaged in a 40-pin 400mil SOJ and 400mil TSOP-2. -25(5V) - ...

Page 2

... IS41C16256 IS41LV16256 FUNCTIONAL BLOCK DIAGRAM OE WE CAS LCAS CLOCK UCAS GENERATOR RAS RAS CLOCK GENERATOR REFRESH COUNTER ADDRESS BUFFERS A0- CONTROL CAS WE LOGICS DATA I/O BUS COLUMN DECODERS SENSE AMPLIFIERS MEMORY ARRAY 262,144 CONTROL LOGIC I/O0-I/O15 Integrated Circuit Solution Inc. DR001-0E 01/25/2002 ...

Page 3

... IS41C16256 IS41LV16256 TRUTH TABLE Function Standby Read: Word Read: Lower Byte Read: Upper Byte Write: Word (Early Write) Write: Lower Byte (Early Write) Write: Upper Byte (Early Write) (1,2) Read-Write (2) EDO Page-Mode Read 1st Cycle: 2nd Cycle: Any Cycle: (1) EDO Page-Mode Write ...

Page 4

... The IS41C16256 and IS41LV16256 CAS function is determined by the first CAS (LCAS or UCAS) transitioning LOW and the last transitioning back HIGH. The two CAS controls give the IS41C16256 both BYTE READ and BYTE WRITE cycle capabilities. Memory Cycle A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH ...

Page 5

... IS41C16256 IS41LV16256 ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Voltage on Any Pin Relative to GND T V Supply Voltage CC I Output Current OUT P Power Dissipation D T Commercial Operation Temperature A Industrial Operationg Temperature T Storage Temperature STG Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

Page 6

... IS41C16256 IS41LV16256 ELECTRICAL CHARACTERISTICS (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter I Input Leakage Current IL I Output Leakage Current IO V Output High Voltage Level OH V Output Low Voltage Level OL I Standby Current: TTL Standby Current: CMOS Operating Current ...

Page 7

... IS41C16256 IS41LV16256 AC CHARACTERISTICS (1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter t Random READ or WRITE Cycle Time RC Access Time from RAS t RAC Access Time from CAS t CAC t Access Time from Column-Address AA RAS Pulse Width t RAS RAS Precharge Time t RP CAS Pulse Width ...

Page 8

... IS41C16256 IS41LV16256 AC CHARACTERISTICS (Continued) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter Column-Address Setup Time to CAS t ACH Precharge during WRITE Cycle OE Hold Time from WE during t OEH READ-MODIFY-WRITE cycle t Data-In Setup Time (15, 22 Data-In Hold Time (15, 22 READ-MODIFY-WRITE Cycle Time ...

Page 9

... IS41C16256 IS41LV16256 Notes initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the (MIN) and V (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V ...

Page 10

... IS41C16256 IS41LV16256 READ CYCLE RAS t CRP UCAS-LCAS t ASR ADDRESS Row WE I/O OE Note: is referenced from rising edge of RAS or CAS, whichever occurs last OFF RAS t CSH t RSH CAS CLCH RCD RAD RAL t t RAH ASC Column t RCS ...

Page 11

... IS41C16256 IS41LV16256 EARLY WRITE CYCLE (OE = DON'T CARE) RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I/O Integrated Circuit Solution Inc. DR001-0E 01/25/2002 RAS t CSH t RSH RCD CAS CLCH RAD RAL RAH ASC CAH t ACH Column t CWL t RWL t WCR t t WCS ...

Page 12

... IS41C16256 IS41LV16256 READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) RAS t CRP UCAS-LCAS t ASR ADDRESS Row WE I RWC t RAS t CSH t t CAS RCD RAD RAH ASC CAH Column t RWD t t RCS CWD t AWD RAC t CAC t CLZ Open ...

Page 13

... IS41C16256 IS41LV16256 EDO-PAGE-MODE READ CYCLE RAS t CRP UCAS/LCAS t t ASR ADDRESS Row t RAH WE Open I/O OE Note: can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the t specifications. PC Integrated Circuit Solution Inc. ...

Page 14

... IS41C16256 IS41LV16256 EDO-PAGE-MODE EARLY-WRITE CYCLE RAS t CRP UCAS/LCAS t RAD t ASR ADDRESS Row t RAH WE I RASP t CSH RCD CAS, CP CAS CLCH CLCH ACH ACH ASC CAH ASC Column Column t t CWL CWL t t WCS ...

Page 15

... IS41C16256 IS41LV16256 EDO-PAGE-MODE READ-WRITE CYCLE RAS t CRP t RCD UCAS/LCAS ASR RAD t t ASC RAH ADDRESS Row t RWD t RCS WE t RAC Open I/O OE Note this diagram is for LATE write cycles only rising edge of CAS to rising edge of CAS. Both measurements must meet the t Integrated Circuit Solution Inc ...

Page 16

... IS41C16256 IS41LV16256 EDO-PAGE-MODE READ-EARLY-WRITE CYCLE RAS t CRP t RCD UCAS/LCAS t t ASR t RAD t t ASC RAH ADDRESS Row t RCS WE t RAC Open I (Psuedo READ-MODIFY WRITE) t RASP t CSH CAS CP CAS CAH ASC CAH Column (A) Column ( CPA ...

Page 17

... IS41C16256 IS41LV16256 AC WAVEFORMS READ CYCLE (With WE-Controlled Disable) RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I/O OE RAS RAS RAS-ONLY REFRESH CYCLE RAS RAS RAS t CRP UCAS/LCAS t ASR ADDRESS I/O Integrated Circuit Solution Inc. DR001-0E 01/25/2002 t CSH t t RCD CAS RAD t t RAH ...

Page 18

... IS41C16256 IS41LV16256 CBR CBR CBR CBR CBR REFRESH CYCLE (Addresses; WE DON'T CARE) RAS t RPC t CP UCAS/LCAS I/O HIDDEN REFRESH CYCLE RAS t CRP UCAS/LCAS t ASR ADDRESS Row I/O OE Notes Hidden Refresh may also be performed after a Write Cycle. In this case LOW and OE = HIGH. ...

Page 19

... IS41C16256-50K 400mil SOJ IS41C16256-50T 400mil TSOP-2 60 IS41C16256-60K 400mil SOJ IS41C16256-60T 400mil TSOP-2 Industrial Range: -40°C to 85°C Speed (ns) Order Part No. 25 IS41C16256-25KI 400mil SOJ IS41C16256-25TI 35 IS41C16256-35KI 400mil SOJ IS41C16256-35TI 50 IS41C16256-50KI 400mil SOJ IS41C16256-50TI 60 IS41C16256-60KI 400mil SOJ IS41C16256-60TI Integrated Circuit Solution Inc. ...

Page 20

... IS41C16256 IS41LV16256 NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, 20 Integrated Circuit Solution Inc. HEADQUARTER: HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5 HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw Integrated Circuit Solution Inc. ...

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