IC61C1024-15K ICSI Integrated Circuit Solution Inc, IC61C1024-15K Datasheet
IC61C1024-15K
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IC61C1024-15K Summary of contents
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... IC61C1024 IC61C1024L Document Title 128K x 8 High-Speed SRAM Revision History Revision No History 0A Initial Draft 0B Revise typo on page 6 and page 8 The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. ...
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... Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IC61C1024 and IC61C1024L are available in 32-pin 300mil SOJ, and 8*20mm TSOP-1, and 8*13.4mm TSOP-1 packages. DECODER ...
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... IC61C1024 IC61C1024L PIN CONFIGURATION 32-Pin SOJ VCC A16 2 31 A15 A14 3 30 CE2 A12 A13 A11 A10 CE1 I/O7 I/ I/O6 I/ I/O5 I/ I/O4 GND 16 17 I/O3 PIN DESCRIPTIONS A0-A16 Address Inputs ...
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... IC61C1024 IC61C1024L ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Terminal Voltage with Respect to GND TERM T Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation Output Current (LOW) OUT Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
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... Current (CMOS Inputs) CE2 ≤ 0.2V V > ≤ 0.2V Note address and data inputs are cycling at the maximum frequency means no input lines change. MAX IC61C1024L POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions I Vcc Operating Supply Current I OUT ...
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... Test conditions assume signal transition times less, timing reference levels of 1.5V, input pulse levels 3.0V and output loading specified in Figure 1. 2. -12 ns device for IC61C1024 only. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. ...
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... IC61C1024 IC61C1024L AC WAVEFORMS READ CYCLE NO. 1 (1,2) ADDRESS D OUT PREVIOUS DATA VALID READ CYCLE NO. 2 (1,3) ADDRESS LZCE HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = V 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. ...
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... Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. -12 ns device for IC61C1024 only. 4. Tested with OE HIGH. 5. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. ...
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... IC61C1024 IC61C1024L AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled HIGH or LOW) ADDRESS DATA UNDEFINED OUT D IN WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) ADDRESS OE CE LOW DATA UNDEFINED OUT D IN Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write ...
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... VALID IN Order Part No. Package IC61C1024-12JI 300mil SOJ IC61C1024-12KI 400mil SOJ IC61C1024-12HI 8*13.4mm TSOP-1 IC61C1024-12TI 8*20mm TSOP-1 IC61C1024-15JI 300mil SOJ IC61C1024-15KI 400mil SOJ IC61C1024-15HI 8*13.4mm TSOP-1 IC61C1024-15TI 8*20mm TSOP-1 IC61C1024-20JI 300mil SOJ IC61C1024-20KI 400mil SOJ IC61C1024-20HI 8*13.4mm TSOP-1 IC61C1024-20TI 8*20mm TSOP-1 IC61C1024-25JI ...
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... IC61C1024L-20H IC61C1024L-20T 25 IC61C1024L-25J IC61C1024L-25K IC61C1024L-25H IC61C1024L-25T NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, Integrated Circuit Solution Inc. AHSR008-0B 10/18/2001 IC61C1024L LOW POWER VERSION ORDERING INFORMATION Industrial Range: –40°C to +85°C Package Speed (ns) 300mil SOJ 15 400mil SOJ 8*13.4mm TSOP-1 8*20mm TSOP-1 300mil SOJ ...