IS42LS16800A ICSI [Integrated Circuit Solution Inc], IS42LS16800A Datasheet
IS42LS16800A
Related parts for IS42LS16800A
IS42LS16800A Summary of contents
Page 1
... IS42S81600A, IS42LS81600A IS42S16800A, IS42LS16800A IS42S32400A, IS42LS32400A 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM FEATURES • Clock frequency: 133 100, MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply ...
Page 2
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A DEVICE OVERVIEW The 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 2.5V V and 1. 3.3V and 3.3V V DDQ DD containing 134,217 ,728 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits ...
Page 3
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A PIN CONFIGURATIONS 54 pin TSOP - Type II for x8 PIN DESCRIPTIONS A0-A11 Row Address Input A0-A8, A10 Column Address Input BA0, BA1 Bank Select Address I/O0 to I/O7 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command ...
Page 4
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A PIN CONFIGURATIONS 54-Ball FBGA for x16 1 A Vss B I/O14 C I/O12 D I/O10 E I/O8 F UDQM G NC/A12 Vss PIN DESCRIPTIONS A0-A11 Row Address Input A0-A8, A10 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ15 Data I/O CLK ...
Page 5
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A PIN CONFIGURATIONS 54 pin TSOP - Type II for x16 PIN DESCRIPTIONS A0-A11 Row Address Input A0-A8, A10 Column Address Input BA0, BA1 Bank Select Address I/O0 to I/O15 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command ...
Page 6
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A PIN CONFIGURATIONS 90-Ball FBGA for x32 1 A I/O26 B I/O28 C VssQ D VssQ E VDDQ F Vss CLK K DQM1 L VDDQ M VssQ N VssQ P I/O11 R I/O13 PIN DESCRIPTIONS A0-A11 Row Address Input A0-A8, A10 Column Address Input BA0, BA1 Bank Select Address ...
Page 7
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A PIN CONFIGURATIONS 86 pin TSOP - Type II for x32 I/O1 I/ I/O3 I/ I/ DQM0 WE CAS RAS CS A11 BA0 BA1 A10 DQM2 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 ...
Page 8
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A PIN FUNCTIONS Symbol Type A0-A11 Input Pin BA0, BA1 Input Pin CAS Input Pin CKE Input Pin CLK Input Pin CS Input Pin I/O0 to I/O Pin I/O32 LDQM, Input Pin UDQM DQM0-DQM3 Input Pin DQM Input Pin RAS ...
Page 9
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A GENERAL DESCRIPTION READ The READ command selects the bank from BA0, BA1 inputs and starts a burst read access to an active row. Inputs A0-A7 provides the starting column location. When A10 is HIGH, this command functions as an AUTO PRECHARGE command ...
Page 10
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A GENERAL DESCRIPTION Continued: The extended mode register has four fields: Options: A11-A7 Drive Strength: A6-A5 Temperature Compensated self Refresh: A4-A3 Partial Array Self Refresh: A2-A0 Following extended mode register programming, no com- mand can be issued before at least 2 CLK have elapsed. ...
Page 11
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A COMMAND TRUTH TABLE CKE Function Symbol n – 1 Device deselect H No operation H × Burst stop H Read H Read with auto precharge H Write H Write with auto precharge H Bank activate H Precharge select bank H Precharge all banks H Mode register set ...
Page 12
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A CKE TRUTH TABLE Current State /Function Activating Clock suspend mode entry Any Clock suspend mode Clock suspend mode exit Auto refresh command Idle Self refresh entry Idle Power down entry Idle Deep power down entry ...
Page 13
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A FUNCTIONAL TRUTH TABLE RAS RAS CAS RAS RAS RAS CAS CAS CAS CAS Idle Row Active ...
Page 14
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A FUNCTIONAL TRUTH TABLE Continued RAS RAS RAS RAS CAS RAS CAS CAS CAS CAS Read with auto H × × Precharging Precharge Precharging ...
Page 15
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A FUNCTIONAL TRUTH TABLE Continued RAS RAS RAS RAS RAS CAS CAS CAS CAS CAS Write Recovering H × × Write Recovering H × ...
Page 16
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A FUNCTIONAL TRUTH TABLE Continued: Notes: 1. All entries assume that CKE is active (CKEn-1=CKEn=H). 2. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 3. Illegal if tRCD is not satisfied. 4. Illegal if tRAS is not satisfied. ...
Page 17
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A STATE DIAGRAM Extended Mode Register Set Mode Register Set Deep Power Down Write CKE WRITE WRITE SUSPEND CKE CKE WRITEA WRITEA SUSPEND CKE Precharge POWER ON Integrated Silicon Solution, Inc. — www.issi.com — ADVANCED INFORMATION Rev. 00A ...
Page 18
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage DD MAX V Maximum Supply Voltage for Output Buffer DDQ MAX +4 Input Voltage IN V Output Voltage OUT P Allowable Power Dissipation D MAX I Output Shorted Current CS T Operating Temperature OPR ...
Page 19
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A DC ELECTRICAL CHARACTERISTICS Symbol Parameter I Input Leakage Current IL I Output Leakage Current OL V Output High Voltage Level Output Low Voltage Level OL I Operating Current (1,2) DD1 I Precharge Standby Current DD2P I (In Power-Down Mode) DD2PS I Precharge Standby Current ...
Page 20
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A DC ELECTRICAL CHARACTERISTICS Symbol Parameter I Auto-Refresh Current DD5 I Self-Refresh Current DD6 PASR=000 (full) PASR=001 (2BK) PASR=010 (1BK) PASR=101 (1/2BK) PASR=110 (1/4BK) I Self-Refresh Current DD6 PASR=000 (full) PASR=001 (2BK) PASR=010 (1BK) PASR=101 (1/2BK) PASR=110 (1/4BK) I Self-Refresh Current ...
Page 21
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Clock Cycle Time CK3 t CK2 (4) t Access Time From CLK AC3 t AC2 t CLK HIGH Level Width CHI t CLK LOW Level Width CL t Output Data Hold Time OH3 t OH2 t Output LOW Impedance Time ...
Page 22
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency t READ/WRITE command to READ/WRITE command CCD t CKE to clock disable or power-down entry mode CKED t CKE to clock enable or power-down exit setup mode PED t DQM to input data delay ...
Page 23
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A AC TEST CONDITIONS Input Load t CHI 1.6V 0.9V CLK 0. 1.6V INPUT 0.9V 0. OUTPUT 0.9V AC TEST CONDITIONS Parameter AC High Level Input Voltage/Low Level Input Voltage Input Rise and Fall Times Input Timing Reference Level Output Timing Measurement Reference Level Integrated Silicon Solution, Inc. — ...
Page 24
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A FUNCTIONAL DESCRIPTION The 128Mb SDRAMs are quad-bank DRAMs which operate at 2.5V or 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. ...
Page 25
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A INITIALIZE AND LOAD MODE REGISTER CLK CKS CKH CKE CMH CMS CMH CMS COMMAND NOP PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 ALL BANKS ...
Page 26
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A AUTO-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK ( High-Z CAS latency = ...
Page 27
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A SELF-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Precharge all active banks refresh mode CAS latency = 2, 3 Integrated Silicon Solution, Inc. — ...
Page 28
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A EXTENDED MODE REGISTER SET CLK CKE H CS RAS CAS WE BA0 BA1 A10 ADD DQM Hi-Z DQ Precharge All Banks Command 28 tRSC 2 CLK (min) Address Key Extended Activated Mode Command Register Set is valid Command Integrated Silicon Solution, Inc. — www.issi.com — ...
Page 29
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS\ latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION ...
Page 30
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A BURST LENGTH Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length deter- mines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst ...
Page 31
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge ...
Page 32
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A CHIP OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank) ...
Page 33
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A READS READ bursts are initiated with a READ command, as shown in the READ COMMAND diagram. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst ...
Page 34
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in the READ to PRECHARGE diagram for each possible CAS latency; data element either the last of a burst of four or the last desired of a longer burst ...
Page 35
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A RW1 - READ TO WRITE CLK DQM COMMAND ADDRESS DQ RW2 - READ TO WRITE WITH EXTRA CLOCK CYCLE T0 CLK DQM COMMAND READ BANK, ADDRESS COL n DQ Integrated Silicon Solution, Inc. — www.issi.com — ADVANCED INFORMATION Rev. 00A 06/01/ ...
Page 36
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A CONSECUTIVE READ BURSTS T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - NOP NOP NOP n+1 OUT OUT NOP NOP READ ...
Page 37
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A RANDOM READ ACCESSES T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com — ADVANCED INFORMATION Rev. 00A 06/01/ READ READ READ BANK, ...
Page 38
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A RW1 - READ TO WRITE CLK DQM COMMAND ADDRESS DQ RW2 - READ TO WRITE WITH EXTRA CLOCK CYCLE T0 CLK DQM COMMAND READ BANK, ADDRESS COL READ NOP NOP BANK, COL NOP NOP NOP t HZ ...
Page 39
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A READ BURST TERMINATION T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com — ADVANCED INFORMATION Rev. 00A 06/01/ ...
Page 40
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A ALTERNATING BANK READ ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK 0 ...
Page 41
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A READ - FULL-PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP READ t CMS DQM/ DQML, DQMH A0-A9, A11 ROW COLUMN A10 ROW BA0, BA1 ...
Page 42
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A READ - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 ...
Page 43
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A READ to PRECHARGE T0 T1 CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com — ADVANCED INFORMATION Rev. 00A ...
Page 44
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A WRITES WRITE bursts are initiated with a WRITE command, as shown in WRITE Command diagram. WRITE COMMAND CLK HIGH CKE CS RAS CAS WE A0-A7 COLUMN ADDRESS A8, A9, A11 AUTO PRECHARGE A10 NO PRECHARGE BA0, BA1 BANK ADDRESS The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access ...
Page 45
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A WRITE BURST COMMAND ADDRESS WRITE TO WRITE RANDOM WRITE CYCLES COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com — ADVANCED INFORMATION Rev. 00A 06/01/ CLK WRITE NOP NOP BANK, COL n CLK COMMAND ...
Page 46
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A WRITE TO READ T0 CLK COMMAND WRITE BANK, ADDRESS COL Latency = 2 WRITE TO PRECHARGE (TWR @ TCK T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL NOP READ NOP BANK, COL b D n+1 IN 15NS ...
Page 47
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A WRITE to PRECHARGE ( CLK DQM COMMAND WRITE BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com — ADVANCED INFORMATION Rev. 00A 06/01/ 15ns NOP NOP PRECHARGE BANK ...
Page 48
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A WRITE - FULL PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD 48 T2 ...
Page 49
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A WRITE - DQM OPERATIOON CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD Integrated Silicon Solution, Inc. — www.issi.com — ...
Page 50
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A ALTERNATING BANK WRITE ACCESS CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 ...
Page 51
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended ...
Page 52
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A CLOCK SUSPEND MODE CLK CKS CKH CKE t t CMS CMH COMMAND READ NOP t t CMS CMH DQM/ DQML, DQMH (2) A0-A9, A11 COLUMN A10 BA0, BA1 BANK DQ CAS latency = 2, burst length = 2 ...
Page 53
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A PRECHARGE The PRECHARGE command (see figure) is used to deac- tivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (t ) after the PRECHARGE RP command is issued. Input A10 determines whether one or ...
Page 54
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A POWER-DOWN MODE CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Two clock cycles Precharge all All banks idle, enter ...
Page 55
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length ...
Page 56
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing (CAS latency) later. The PRECHARGE to bank n will begin after t where t begins when the READ to bank m is registered. ...
Page 57
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A SINGLE READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD ...
Page 58
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK ...
Page 59
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A SINGLE READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW DISABLE AUTO PRECHARGE BA0, BA1 ...
Page 60
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK ...
Page 61
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A SINGLE READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD ...
Page 62
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A SINGLE WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 ...
Page 63
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK ...
Page 64
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW ...
Page 65
... MHz 10 IS42LS81600A-10TI 54pin TSOPII Frequency Speed (ns) Order Part No. 133 MHz 7 IS42LS16800A-7BI IS42LS16800A-7TI 100 MHz 10 IS42LS16800A-10BI IS42LS16800A-10TI 54 Pin TSOPII Frequency Speed (ns) Order Part No. 133 MHz 7 IS42LS32400A-7BI IS42LS32400A-7TI 100 MHz 10 IS42LS32400A-10BI IS42LS32400A-10TI 86-Pin TSOPII Integrated Silicon Solution, Inc. — www.issi.com — ADVANCED INFORMATION Rev. 00A 06/01/ ...
Page 66
... IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A ORDERING INFORMATION - V Commercial Range Frequency Speed (ns) Order Part No. 133 MHz 7 IS42S81600A-7T 100 MHz 10 IS42S81600A-10T Frequency Speed (ns) Order Part No. 133 MHz 7 IS42S16800A-7B IS42S16800A-7T 100 MHz 10 IS42S16800A-10B IS42S16800A-10T Frequency Speed (ns) Order Part No. 133 MHz 7 IS42S32400A-7B ...