AT52SC1283J-70CI ATMEL [ATMEL Corporation], AT52SC1283J-70CI Datasheet - Page 6

• Manufacturer Part Number: AT52SC1283J-70CI
• Description: 128-Mbit Flash + 32-Mbit/64-Mbit
• Manufacturer: ATMEL [ATMEL Corporation]

6.7
6.8
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Fixed-Length Burst Reads
Burst Suspend
AT52SC1283J/1284J [Preliminary]
takes place only once, and only if the burst sequence crosses a 16-word boundary. To indicate
that the device is not ready to continue the burst, the device will drive the WAIT pin low (B10 and
B8 = 0) during the clock cycles in which new data is not being presented. Once the WAIT pin is
driven high (B10 and B8 = 0), the current data will be valid. The WAIT signal will be tri-stated
when the CE or OE signal is high.
In the “Burst Read Waveform” as shown on
the specified clock latency of three, data D13 is valid within 13 ns of clock edge B. The low-to-
high transition of the clock at point C results in D14 being read. The transition of the clock at
point D results in a burst read of D15. The clock transition at point E does not cause new data to
appear on the output lines because the WAIT signal goes low (B10 and B8 = 0) after the clock
transition, which signifies that the first boundary in the memory has been crossed and that new
data is not available. After a clock latency of three, the clock transition at point F does cause a
burst read of data D16 because the WAIT signal goes high (B10 and B8 = 0) after the clock tran-
sition indicating that new data is available. Additional clock transitions, like at point G, will
continue to result in burst reads.
During a fixed-length burst mode read, four, eight or sixteen words of data may be burst from the
device, depending upon the configuration. The device supports a linear burst mode. The burst
sequence is shown on
burst wrap bit (B3 = 1) set, the device may incur an output delay when the burst sequence
crosses the first 16-word boundary in the memory. If the starting is D0 - D12, there is no delay. If
the starting address is D13 - D15, an output delay equal to the initial clock latency is incurred.
The delay takes place only once, and only if the burst sequence crosses a 16-word boundary.
To indicate that the device is not ready to continue the burst, the device will drive the WAIT pin
low (B10 and B8 = 0) during the clock cycles in which new data is not being presented. Once the
WAIT pin is driven high (B10 and B8 = 0), the current data will be valid. The WAIT signal will be
tri-stated when the CE or OE signal is high.
The “Four-word Burst Read Waveform” on
valid address is latched at point A. For the specified clock latency of four, data D0 is valid within
13 ns of clock edge B. The low-to-high transition of the clock at point C results in D1 being read.
Similarly, D2 and D3 are output following the next two clock cycles. Returning CE high ends the
read cycle. There is no output delay in the burst access wrap mode (B3 = 0).
The Burst Suspend feature allows the system to temporarily suspend a synchronous burst oper-
ation if the system needs to use the Flash address and data bus for other purposes. Burst
accesses can be suspended during the initial latency (before data is received) or after the device
has output data. When a burst access is suspended, internal array sensing continues and any
previously latched internal data is retained.
Burst Suspend occurs when CE is asserted, the current address has been latched (either rising
edge of AVD or valid CLK edge), CLK is halted, and OE is deasserted. The CLK can be halted
when it is at V
Subsequent CLK edges resume the burst sequence where it left off.
Within the device, OE gates the WAIT signal. Therefore, during Burst Suspend the WAIT signal
reverts to a high-impedance state when OE is deasserted.
page 34.
IH
or V
IL
. To resume the burst access, OE is reasserted and the CLK is restarted.
page
22. When operating in the linear burst read mode (B7 = 1) with the
page
page 34
33, the valid address is latched at point A. For
illustrates a fixed-length burst cycle. The
See “Burst Suspend Waveform” on
3530B–STKD–2/4/05