AT52SC1283J-70CI ATMEL [ATMEL Corporation], AT52SC1283J-70CI Datasheet - Page 30

• Manufacturer Part Number: AT52SC1283J-70CI
• Description: 128-Mbit Flash + 32-Mbit/64-Mbit
• Manufacturer: ATMEL [ATMEL Corporation]

18. AC Asynchronous Read Timing Characteristics
19. AVD Pulsed Asynchronous Read Cycle Waveform
Notes:
20. Asynchronous Read Cycle Waveform
Notes:
30
Symbol
t
t
t
t
t
t
t
t
t
t
t
ACC1
ACC2
CE
OE
AHAV
AVLP
AVHP
AAV
DF
OH
RO
1. After the high-to-low transition on AVD, AVD may remain low as long as the address is stable.
2. CLK may be static high or static low.
1. CE may be delayed up to t
2. OE may be delayed up to t
3. t
4. AVD and CLK should be tied low.
AT52SC1283J/1284J [Preliminary]
without impact on t
DF
is specified from OE or CE, whichever occurs first (CL = 5 pF).
Parameter
Access, AVD To Data Valid
Access, Address to Data Valid
Access, CE to Data Valid
OE to Data Valid
Address Hold from AVD
AVD Low Pulse Width
AVD High Pulse Width
Address Valid to AVD
CE, OE High to Data Float
Output Hold from OE, CE or Address, Whichever Occurred First
RESET to Output Delay
ACC
.
I/O0-I/O15
A2 -A22
RESET
A0 -A1
ACC
CE
AVD
OE
CE
(1)
- t
I/O0 - I/O15
- t
OE
A0 - A22
t AVLP
CE
RESET
after the falling edge of CE without impact on t
OE
CE
after the address transition without impact on t
t AVHP
t AAV
t AAV
t RO
t ACC2
t ACC2
t ACC1
t CE
t AHAV
t AHAV
HIGH Z
t OE
t
ACC2
t
ADDRESS VALID
RO
t
CE
t
OE
t
RC
(1)(2)(3)(4)
DATA VALID
OUTPUT
VALID
t
OH
t
DF
(1)(2)
t DF
t DF
CE
Min
ACC
10
10
9
7
or by t
.
ACC
- t
OE
Max
150
70
70
70
20
25
after an address change
3530B–STKD–2/4/05
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns